The post Ideal Operational Amplifier appeared first on Electrical A2Z.

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**Figure 1 **Typical digital audio player

Amplifiers have important applications in practically every field of engineering because the vast majority of transducers and sensors used for measurement produce electrical signals, which are then amplified, filtered, sampled, and processed by analog and digital electronic instrumentation. **For example**, mechanical engineers use thermistors, accelerometers, and strain gauges to convert temperature, acceleration, and strain into electrical signals. These signals must be amplified prior to transmission and then filtered (a function carried out by amplifiers) prior to sampling the data in preparation for producing a digital version of the original analog signal.

Other, less obvious, functions such as impedance isolation are also performed by amplifiers. It should now be clear that amplifiers do more than simply produce an enlarged replica of a signal although that function is certainly very important.

The simplest model for an amplifier is depicted in **Figure 2,** where a signal *v _{S}* is amplified by a constant factor

\[\begin{matrix}{{v}_{0}}=G{{v}_{in}}=G{{v}_{S}} & Ideal\text{ }amplifier & (1) \\\end{matrix}\]

**Figure 2 **Amplifier between source and load

Note that the input seen by the amplifier is a Thevenin source (*v _{S}* in series with

A more realistic (but still quite simple) amplifier model is shown in **Figure 3**. In this figure the concepts of input and output impedance of the amplifier are incorporated as single resistances *R*_{in} and *R*_{out}, respectively. That is, from the perspective of the load *R* the amplifier acts as a Thevenin source (*A* *υ*_{in} in series with *R*_{out}), while from the perspective of the external source (*v _{S}* in series with

**Figure 3 **Simple voltage amplifier model

Using the amplifier model of **Figure 3** and applying voltage division, the input voltage to the amplifier is now:

\[{{v}_{ab}}={{v}_{in}}=\frac{{{R}_{in}}}{{{R}_{S}}+{{R}_{in}}}{{v}_{S}}\begin{matrix}{} & {} & (2) \\\end{matrix}\]

The output voltage of the amplifier can also be found by applying voltage division, where:

\[{{v}_{0}}=A{{v}_{in}}\frac{R}{{{R}_{out}}+R}\begin{matrix}{} & {} & (3) \\\end{matrix}\]

Substitute for *v*_{in} and divide both sides by *v _{S}* to obtain:

\[\frac{{{v}_{0}}}{{{v}_{S}}}=A\frac{{{R}_{in}}}{{{R}_{S}}+{{R}_{in}}}\frac{R}{{{R}_{out}}+R}\begin{matrix}{} & {} & (4) \\\end{matrix}\]

which is the overall voltage gain from *v _{S}* to

\[G=\frac{{{v}_{0}}}{{{v}_{in}}}=A\frac{R}{{{R}_{out}}+R}\begin{matrix}{} & {} & (5) \\\end{matrix}\]

For this model, the voltage gain *G* is dependent upon the external resistance *R*, which means that the amplifier performs differently for different loads. Moreover, the input voltage *v*_{in} to the amplifier is a modified version of *v _{S}*. Neither of these results seem desirable. Rather, it stands to reason that the gain of a “quality” amplifier would be independent of its load and would not impact its source signal. These attributes are achieved when

\[\underset{{{R}_{out}}\to 0}{\mathop{\lim }}\,\frac{R}{{{R}_{out}}+R}=1\begin{matrix}{} & {} & (6) \\\end{matrix}\]

such that:

\[G\equiv \frac{{{v}_{0}}}{{{v}_{in}}}\approx A\begin{matrix}{} & when\begin{matrix}{} & {{R}_{out}}\to 0 \\\end{matrix} \\\end{matrix}\begin{matrix}{} & {} & (7) \\\end{matrix}\]

Also, in the limit that *R*_{in} → ∞:

\[\underset{{{R}_{in}}\to \infty }{\mathop{\lim }}\,\frac{{{R}_{in}}}{{{R}_{in}}+{{R}_{S}}}=1\begin{matrix}{} & {} & (8) \\\end{matrix}\]

such that

\[{{v}_{in}}\approx {{v}_{S}}\begin{matrix}{} & when\begin{matrix}{} & {{R}_{in}}\to \infty \\\end{matrix} \\\end{matrix}\begin{matrix}{} & {} & (9) \\\end{matrix}\]

In general, a “quality” voltage amplifier will have a very small output impedance and a very large input impedance.

**Input and Output Impedance**

In general, the input impedance *R*_{in} and the output impedance *R*_{out} of an amplifier are defined as:

\[{{R}_{in}}=\frac{{{v}_{in}}}{{{i}_{in}}}\begin{matrix}{} & and\begin{matrix}{} & {{R}_{out}}=\frac{{{v}_{OC}}}{{{i}_{SC}}} \\\end{matrix} \\\end{matrix}\begin{matrix}{} & {} & (10) \\\end{matrix}\]

where *v _{OC}* is the open-circuit voltage and

It is a worthwhile exercise to show that an ideal *current amplifier* has zero input impedance and infinite output impedance. Also, an ideal *power amplifier* is designed so that its input impedance matches its source network and its output impedance matches its load impedance.

**Feedback**

Feedback, which is the process of using the output of an amplifier to reinforce or inhibit its input, plays a critical role in many amplifier applications.

Without feedback an amplifier is said to be in *open*–*loop* mode; with feedback an amplifier is said to be in *closed*–*loop* mode. The output of the amplifier model shown in **Figure 3** does not affect its input (because there is no path from output to input), so feedback is not present, and the model is open-loop.

As suggested earlier, the most basic characteristic of an amplifier is its *gain*, which is simply the ratio of the output to the input. The open-loop gain *A* of a practical amplifier (e.g., an operational amplifier) is usually very large, whereas the closed-loop gain *G* is a reduced version of the open-loop gain.

There are **two types of feedback** possible in closed-loop mode: ** positive feedback**, which tends to reinforce the amplifier input, and

In general, negative feedback causes the large open-loop gain *A* of an amplifier to be exchanged for a smaller closed-loop gain *G*. While this exchange may seem undesirable at first glance, several key benefits accompany the exchange. These benefits to the amplifier are:

- Decreased sensitivity to variations in circuit and environmental parameters, most notably temperature.
- Increased bandwidth.
- Increased linearity.
- Increased signal-to-noise ratio.

In addition, negative feedback is implemented by establishing one or more paths from the output to the input of the amplifier. The impedance of each feedback path can be adjusted to produce improved input and output impedances of the overall amplifier circuit. These input and output impedances are key characteristics for understanding the *loading effects* of other circuits attached to an amplifier.

**Figure 4** shows a *signal*–*flow diagram* of an amplifier situated between a source and a load. The arrows indicate the direction of signal flow. The signals shown are *u _{s}*,

\[y=Ae\begin{matrix}{} & and\begin{matrix}{} & {{u}_{f}}=\beta y \\\end{matrix} \\\end{matrix}\begin{matrix}{} & {} & (11) \\\end{matrix}\]

**Figure 4 **Signal-flow diagram of generic amplifier

The circle sums its inputs, *u _{s}* and

\[e\begin{matrix}={{u}_{s}} & \begin{matrix}- & {{u}_{f}}={{u}_{s}}-\beta y \\\end{matrix} \\\end{matrix}\begin{matrix}{} & {} & (12) \\\end{matrix}\]

Because the feedback signal *u _{f}* makes a negative contribution to the sum, the signal flow diagram of

**Equations 11 and 12** can be combined to yield:

\[\begin{matrix}y=Ae= & \begin{matrix}A({{u}_{s}}- & {{u}_{f}})=A({{u}_{s}}-\beta y \\\end{matrix}) \\\end{matrix}\begin{matrix}{} & {} & (13) \\\end{matrix}\]

which can be rearranged to solve for *y*. Then, the closed-loop gain of the amplifier is:

\[G\equiv \frac{y}{{{u}_{s}}}=\frac{A}{1+A\beta }\begin{matrix}{} & {} & (14) \\\end{matrix}\]

The quantity *Aβ* is known as the *loop gain.* Implicit in the derivation of equation 14 is that the behavior of the blocks within the amplifier is not affected by the other blocks nor by the external source and load. In other words, the blocks are *ideal* such that ** loading effects are zero**.

Two important observations can be made at this point:

- The closed-loop gain
*G*depends upon*β*, which is known as the*feedback factor.* - Since
*Aβ*is positive, the closed-loop gain*G*is smaller than the open-loop gain*A.*

Furthermore, for most practical amplifiers, *Aβ* is quite large such that:

\[G\approx \frac{1}{\beta }\begin{matrix}{} & {} & (15) \\\end{matrix}\]

This result is particularly important (and probably surprising!) because it indicates that the closed-loop gain *G* of the amplifier is largely *independent* of the open-loop gain A, as long as *Aβ ≫* 1, and that *G* is, in turn, determined largely by the feedback factor, *β.*

When *Aβ ≫* 1, the closed-loop gain *G* of an amplifier is determined largely by the feedback factor, *β*.

Furthermore, **equation 14** can be used to find the ratio of the two inputs, *u _{s}* and

\[\frac{{{u}_{f}}}{{{u}_{s}}}=\frac{y}{{{u}_{s}}}\frac{{{u}_{f}}}{y}=\frac{A}{1+A\beta }\beta =\frac{A\beta }{1+A\beta }\begin{matrix}{} & {} & (16) \\\end{matrix}\]

Thus, when *Aβ ≫* 1, another important result is:

\[\frac{{{u}_{f}}}{{{u}_{s}}}\to 1\begin{matrix}{} & or\begin{matrix}{} & {{u}_{s}}-{{u}_{f}}\to 0 \\\end{matrix} \\\end{matrix}\begin{matrix}{} & {} & (17) \\\end{matrix}\]

This result indicates that when the loop gain *Aβ* is large, the *difference* between the input signal *u _{s}* and the feedback signal

When *Aβ ≫* 1, the *difference* between the input signal *u _{s}* and the feedback signal

Both of the results of **equations 15 and 17** will show up repeatedly in the analysis of operational amplifier circuits in closed-loop mode.

**Benefits of Negative Feedback**

Negative feedback provides several benefits in exchange for a reduced gain. For example, take the derivative of both sides of** equation 14** to find:

\[dG=\frac{dA}{1+A\beta }-\frac{A\beta dA}{{{(1+A\beta )}^{2}}}=\frac{dA}{{{(1+A\beta )}^{2}}}\begin{matrix}{} & {} & (18) \\\end{matrix}\]

Divide the left side by *G* and the right side by *A*/(1 + *Aβ*) to obtain:

\[\frac{dG}{G}=\frac{1}{1+A\beta }\frac{dA}{A}\begin{matrix}{} & {} & (19) \\\end{matrix}\]

When *Aβ ≫* 1, this result indicates that the percentage change in *G* due to a percentage change in *A* is relatively small. In other words, the closed-loop gain *G* is relatively insensitive to changes in the open-loop gain *A.*

When *Aβ ≫* 1, the closed-loop gain *G* is relatively insensitive to changes in the open-loop gain *A.*

For any amplifier, the open-loop gain *A* is a function of frequency. For example, the open-loop gain *A*(*ω*) of an op-amp is characterized by a simple pole such that:

\[A(\omega )=\frac{{{A}_{0}}}{1+j\omega /{{\omega }_{0}}}\begin{matrix}{} & {} & (20) \\\end{matrix}\]

where *ω _{o}* is its 3-dB break frequency. The Bode magnitude characteristic plot is shown in

\[G(\omega )=\frac{A(\omega )}{1+A(\omega )\beta }=\frac{{{A}_{0}}(1+j\omega /{{\omega }_{0}})}{1+{{A}_{0}}\beta (1+j\omega /{{\omega }_{0}})}\begin{matrix}{} & {} & (21) \\\end{matrix}\]

**Figure 5 **Typical amplifier Bode magnitude characteristic

Multiply the numerator and denominator on the right side of equation 21 by 1 + *jω*/*ω _{o}* and then factor out 1 +

\[G(\omega )=\frac{{{A}_{o}}}{1+{{A}_{o}}\beta }\frac{1}{1+{j\omega }/{{{\omega }_{g}}}\;}={{G}_{0}}\frac{1}{1+j\omega /{{\omega }_{g}}}\begin{matrix}{} & {} & (22) \\\end{matrix}\]

Where *ω _{g}* =

The closed-loop 3-dB break frequency is (1 + *A*_{0}*β*) larger than the open-loop 3-dB break frequency.

Likewise, if the amplifier is characterized by a simple zero, its 3-dB break frequency will be (1 + *A*_{0}*β*) *smaller* than the open-loop 3-dB break frequency. It is a worthwhile exercise to work out this result.

Similar analyses can be performed to show the increased linearity and increased signal-to-noise ratio resulting from negative feedback. All these benefits are acquired at the expense of amplifier gain. Finally, all of the features of a generic amplifier with negative feedback outlined in this section also occur in closed-loop amplifiers constructed using operational amplifiers and other basic components.

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]]>Zener diodes are designed and intended to be used when reverse-biased. The basic mechanism behind the Zener reverse breakdown effect was described **here**. It is important to recall that the mechanisms behind the Zener and avalanche reverse breakdown effects are different. This difference accounts for the difference in the range of breakdown voltages *V _{Z}* within which each effect dominates. For Zener diodes,

A generic diode *i-v* characteristic, with forward offset voltage *V*_{𝛾} and **reverse breakdown voltage ***V*_{Z}. Note the steep slope of the *i-v* characteristic near *V _{Z}*, which suggests that when

Although the slope of the *i-v* characteristic is not constant near −*V _{Z}*, for the sake of simplicity in introducing the basic principles of voltage regulation this slope will be assumed to be constant such that a Zener diode can be modeled with linear elements when it is reverse-biased near

Like other diodes, a Zener diode has three regions of operation:

- When
*v*≥_{D}*V*, the Zener diode is forward-biased and can be analyzed using the piecewise linear model shown in_{γ}**Figure 1.**

**Figure 1 **Zener diode model for forward bias

- When −
*V*<_{Z}*v*<_{D}*V*, the Zener diode is reverse-biased but has not reached breakdown. In this region, it can be modeled as an open-circuit._{γ} - For
*v*≤_{D}*–V*, the Zener diode is reverse-biased and breakdown has ensued. In this region, it can be modeled using the piecewise linear model shown in_{Z}**Figure 2.**

**Figure 2 **Zener diode model for reverse bias

The combined effect of forward and reverse bias may be lumped into a single model with the aid of ideal diodes, as shown in **Figure 3.**

**Figure 3 **Complete model for Zener diode

To illustrate the operation of a Zener diode as a voltage regulator, consider the circuit of **Figure 4(a),** where the unregulated DC source *V _{S}* is regulated to the value of the Zener voltage

Note how the diode must be connected upside down to obtain a positive regulated voltage. Also note that when *v _{S}* >

The source resistance *R _{S}* is essential because it allows the voltage difference

**Figure 4 **(a) A Zener diode voltage regulator circuit diagram; and (b) the simplest equivalent circuit

**Three observations** are sufficient to understand the operation of this voltage regulator:

**1.**The load voltage must equal *V _{Z}* as long as the Zener diode is in the reverse breakdown mode. Then:

\[i=\frac{{{V}_{Z}}}{R}\begin{matrix}{} & {} & (1) \\\end{matrix}\]

**2.**The output current is the nearly constant difference between the unregulated supply current *i _{S}* and the diode current

\[i={{i}_{S}}-{{i}_{Z}}\begin{matrix}{} & {} & (2) \\\end{matrix}\]

Any current in excess of that required to keep the load at the constant voltage *V _{Z}* is sent to ground through the diode. Thus, the Zener diode acts as a sink for any undesired source current.

**3.**The source current is:

\[{{i}_{S}}=\frac{{{v}_{S}}-{{V}_{Z}}}{{{R}_{S}}}\begin{matrix}{} & {} & (3) \\\end{matrix}\]

There are certain considerations that arise in the design of a practical voltage regulator. One of these considerations is the power rating of the diode. The power *P _{Z}* dissipated by the diode is:

\[{{P}_{Z}}={{i}_{Z}}{{V}_{Z}}\begin{matrix}{} & {} & (4) \\\end{matrix}\]

Since *V _{Z}* is more or less constant, the power rating establishes an upper limit on the allowable diode current

**Another significant limitation** occurs when the load resistance is small, thus requiring large amounts of current from the unregulated supply. In this case, the Zener diode is hardly taxed at all in terms of power dissipation, but the unregulated supply may not be able to provide the current required to sustain the load voltage. In this case, regulation fails to take place. Thus, in practice, the range of load resistances for which load voltage regulation may be attained is constrained to a finite interval:

\[{{R}_{\min }}\le R\le {{R}_{\max }}\begin{matrix}{} & {} & (5) \\\end{matrix}\]

Where *R*_{max} is typically limited by the Zener diode power rating and *R*_{min} by the maximum supply current.

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]]>The post PN Junction Theory for Semiconductor Diodes appeared first on Electrical A2Z.

]]>**Figure 1** depicts an idealized PN junction. The difference in concentrations of free electrons in the n-type material compared to the p-type material results in a diffusion of free electrons from right to left across the junction. **Likewise**, the difference in concentration of holes on either side of the junction results in diffusion of holes from left to right across the junction.

In both cases, the **diffusion current** I_{d} is directed left to right because a positive current is defined as either positive holes moving left to right or negative free electrons moving right to left.

**Figure 1 **A PN junction

As free electrons leave the n-type material and enter the p-type material they tend to recombine with holes. Likewise, as holes leave the p-type material and enter the n-type material they tend to recombine with free electrons.

Once free electrons and holes recombine, they are no longer mobile, but held in place in the material lattice by covalent bonds.

At first, most of the recombination occur close to the junction. However, as time passes, more and more of the mobile charges near the junction have recombined such that diffusing mobile charges must travel further from the junction to encounter a partner with which to recombine. Thus, this diffusion process results in recombination on both sides of the junction and, as the process continues, an expanding **depletion region** wherein virtually no mobile charge carriers remain. This region is electrically charged because mobile charge carriers that have recombined to form the region have no electrical counterpart in the lattice where they have become fixed. In **Figure 1** this result is depicted by the negatively charged p-type region to the left of the junction and the positively charged n-type region to the right of the junction.

Once the depletion region begins to form, the resulting net charge separation produces an electric field pointing from the positively charged n-type to the negatively charged p-type portions of the depletion region. This electric field slows the ongoing diffusion of majority charge carriers by establishing a **potential barrier** or **contact potential** across the depletion region. This potential depends upon the semiconductor material (about 0.6 to 0.7 V for silicon) and is also known as the offset voltage V_{γ}.

In addition to the diffusion current associated with majority charge carriers, an oppositely directed **drift current** I_{S }associated with minority charge carriers is established across the depletion region.

Specifically, free electrons and holes are thermally generated in the p- and n-type materials, respectively. Any of these minority carriers that manage to reach the depletion region are swept across it by the electric field.

Note that both components of the drift current contribute to a positive current from right to left because a positive current is defined as either positive hole moving right to left or negative free electrons moving left to right.

**Figure 2** depicts the presence of both a diffusion current and drift current across the depletion region. Its equilibrium width is reached when the average net drift current exactly offsets the average net diffusion current.

Recall that the magnitude of the diffusion current is largely determined by the concentration of the donor and acceptor elements while the magnitude of the drift current is highly temperature dependent. Thus, the equilibrium width of the depletion region depends upon both temperature and the doping process.

**Figure 2 **Drift and diffusion currents in a PN junction

Now consider the case shown in **Figure 3(a)** where a battery has been connected across a PN junction in the **reverse-biased** direction. Assume that suitable contacts between the battery and the p- and n-type materials are established.

The reverse-bias orientation of the battery widens the depletion region and increases the potential barrier across it such that the majority carrier diffusion current decreases.

On the other hand, the minority carrier drift current increases such that there is now a small (on the order of nano-amperes) non-zero current I_{0} directed from the n- to p-type region. I_{0} is small because it is comprised of minority carriers. Thus, when reverse-biased, the diode current i_{D} is:

${{i}_{D}}=-{{I}_{0}}={{I}_{S}}$ Reverse-based diode current

Where I_{S} is known as the **reverse saturation current.**

When the PN junction is forward-biased as in **Figure 3(b),** the depletion region is narrowed and the potential barrier across it is lowered such that the majority carrier diffusion current increases. As the forward-biased diode voltage v_{D} is increased the diffusion current I_{d} increases exponentially:

\[{{I}_{d}}={{I}_{0}}{{e}^{{{q}_{e}}{{v}_{D}}/kT}}={{I}_{0}}{{e}^{{{v}_{D}}/{{V}_{T}}}}\begin{matrix}{} & {} & (1) \\\end{matrix}\]

Where q_{e} = 1.6 × 10^{−19} C is the elementary charge, T is the material temperature (in K), and V_{T} = kT/q_{e} is the **thermal voltage.** At room temperature, V_{T} ≈ 25 mV. The net diode current under forward bias is:

\[{{i}_{D}}={{I}_{d}}-{{I}_{0}}={{I}_{0}}({{e}^{{{v}_{D}}/{{V}_{T}}}}-1)\begin{matrix}{} & Diode\text{ }Equation & (2) \\\end{matrix}\]

**Figure 3 **Forward- and reverse-biased PN junctions

**Figure 4** depicts the diode i-v characteristic described by the diode equation for a fairly typical silicon diode for v_{D} > 0. Since I_{0} is typically very small (10^{−9} to 10^{−15} A), the diode equation is often approximated by:

\[{{i}_{D}}={{I}_{0}}{{e}^{{{v}_{D}}/{{V}_{T}}}}\begin{matrix}{} & {} & (3) \\\end{matrix}\]

This expression is a good approximation for a silicon diode at room temperature when v_{D} is greater than a few tenths of a volt.

**Figure 4 **Typical diode i-v characteristic curve

The ability of the PN junction to conduct significant current only in the forward-biased direction allows it to function in electric circuits much like a check valve functions in mechanical circuits. A generic PN junction and the diode circuit symbol are shown in **Figure 5.** Notice that the triangle shape suggests the direction of forward-biased current. Positive current i_{D} passes from the **anode** to the **cathode,** where the term cathode always refers to the source of electrons (negative charge carriers) whether used in reference to a diode or battery.

**Figure 5 **Diode circuit symbol

**Figure 6** shows the complete i-v characteristic of a diode. Note that the diode current is approximately zero when v_{D} < 0 unless v_{D} is sufficiently large and negative (reverse-biased) such that **reverse breakdown** occurs. When v _{D} < − V_{Z}, the diode conducts current in the reverse-biased direction. **Two effects** contribute to this reverse-biased current: the Zener effect and avalanche breakdown. In silicon diodes, the Zener effect tends to dominate when V_{Z} < 5.6 V while avalanche breakdown tends to dominate at larger, more negative diode voltages.

**Figure 6 **The diode i-v characteristic

The root causes of these two effects, while similar, are not the same. The Zener effect is significant when the depletion region is designed to be heavily doped but very thin such that for a given potential difference v_{D}, the electric field is large enough to sever covalent bonds in the depletion region and generate pairs of free electrons and holes, which are then swept away by the electric field, thus creating a current.

**Avalanche breakdown** occurs when the potential difference v_{D} is large enough that the kinetic energy of minority charge carriers is sufficient to break covalent bonds during collisions. These collisions may liberate free electrons and holes, which, again, are swept away by the electric field.

The process by which energy is imparted to new charge carriers is called **impact ionization**. These new charge carriers may also have enough energy to energize other low-energy electrons, such that a sufficiently large reverse-biased diode voltage may initiate an avalanche of liberated charge carriers.

In **Zener breakdown** the high concentration of charge carriers provides the means for a substantial reverse-biased current to be sustained, at a nearly constant reverse-biased voltage, the **Zener voltage** V_{Z}. This effect is very useful in applications where one would like to regulate (hold constant) the voltage across a load.

It should also be noted that a typical silicon diode is not designed for use in reverse breakdown, where even a modest current at a large V_{Z} will likely generate more power than the diode can dissipate through heat transfer. The result could be a melted or burned diode!

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]]>

**Figure a:** Operational Amplifier

**Voltage Supply Limits**

As indicated in **Figure a**, operational amplifiers (and all amplifiers, in general) are powered by external DC voltage supplies *V _{S}*

The effect of limiting supply voltages is that amplifiers are capable of amplifying signals *only within the range of their supply voltages*; it would be physically impossible for an amplifier to generate a voltage greater than *V _{S}*

\[{{V}_{S}}^{-}<{{v}_{0}}<{{V}_{S}}^{+}\begin{matrix}{} & {} & (1) \\\end{matrix}\]

For most op-amps, the limit is actually approximately 1.5 V less than the supply voltages. How does this practically affect the performance of an amplifier circuit? An example will best illustrate the idea.

Note how the voltage supply limit actually causes the peaks of the sine wave to be clipped in an abrupt fashion. This type of hard nonlinearity changes the characteristics of the signal quite radically and could lead to significant errors if not taken into account.

Just to give an intuitive idea of how such clipping can affect a signal, have you ever wondered why rock guitar has a characteristic sound that is very different from the sound of classical or jazz guitar? The reason is that the “rock sound” is obtained by over-amplifying the signal, attempting to exceed the voltage supply limits, and causing clipping similar in quality to the distortion introduced by voltage supply limits in an op-amp. This clipping broadens the spectral content of each tone and causes the sound to be distorted.

One of the circuits most directly affected by supply voltage limitations is the op-amp integrator.

**Frequency Response Limits**

Another property of all amplifiers that may pose severe limitations to the op-amp is their finite bandwidth. We have so far assumed, in our **ideal op-amp model**, that the open-loop gain is a very large constant. In reality, *A* is a function of frequency and is characterized by a low-pass response. For a typical op-amp,

\[A(j\omega )=\frac{{{A}_{0}}}{1+j\omega /{{\omega }_{0}}}\begin{matrix}{} & Finite\text{ }bandwidth\text{ }limitation & (2) \\\end{matrix}\]

The cutoff frequency of the op-amp open-loop gain ω_{0} represents approximately the point where the amplifier response starts to drop off as a function of frequency and is analogous to the cutoff frequencies of the RC and RL circuits.

**Figure 1** depicts A (jω) in both linear and decibel plots for the fairly typical values A_{0} = 10^{6 }and ω_{0} = 10π. It should be apparent from **Figure 1** that the assumption of a very large open-loop gain becomes less and less accurate for increasing frequency. Recall the initial derivation of the closed-loop gain for the **inverting amplifier**: In obtaining the final result **V**_{o}/**V**_{S} = −R_{F}/R_{S}, it was assumed that A → ∞. This assumption is clearly inadequate at the higher frequencies.

**Figure 1 **Open-loop gain of practical op-amp (a) amplitude ratio response; (b) dB response

The finite bandwidth of the practical op-amp results in a fixed gain-bandwidth product for any given amplifier. The effect of a constant gain-bandwidth product is that as the closed-loop gain of the amplifier is increased, its 3-dB bandwidth is proportionally reduced until, in the limit, if the amplifier were used in the **open-loop mode**, its gain would be equal to A_{0} and its 3-dB bandwidth would be equal to ω_{0}. The constant gain-bandwidth product is therefore equal to the product of the open-loop gain and the open-loop bandwidth of the amplifier: A_{0}ω_{0} = K.

When the amplifier is connected in a **closed-loop configuration** (e.g., as an inverting amplifier), its gain is typically much less than the open-loop gain and the 3-dB bandwidth of the amplifier is proportionally increased. To explain this further, **Figure 2** depicts the case in which two different linear amplifiers (achieved through any two different negative feedback configurations) have been designed for the same op-amp. The first has closed-loop gain G_{1} = A_{1}, and the second has closed-loop gain G_{2} = A_{2}.

The bold line in the **figure** indicates the open-loop frequency response, with gain A_{0} and cutoff frequency ω_{0}. As the gain decreases from A_{0} to A_{1}, the cutoff frequency increases from ω_{0} to ω_{1}. As the gain decreases to A_{2}, the bandwidth increases to ω_{2}. Thus:

The gain-bandwidth product of any given op-amp is constant.

\[{{A}_{0}}\times {{\omega }_{0}}={{A}_{1}}\times {{\omega }_{1}}={{A}_{2}}\times {{\omega }_{2}}=K\begin{matrix}{} & {} & (3) \\\end{matrix}\]

**Figure 2**

**Input Offset Voltage**

Another limitation of practical op-amps results because even in the absence of any external inputs, it is possible that an offset voltage will be present at the input of an op-amp. This voltage is usually denoted by ±V_{os}, and it is caused by mismatches in the internal circuitry of the op-amp.

The offset voltage appears as a differential input voltage between the inverting and non-inverting input terminals. The presence of an additional input voltage will cause a DC bias error in the amplifier output.

Typical and maximum values of V_{os} are quoted in manufacturers’ data sheets. The worst-case effects due to the presence of offset voltages can therefore be predicted for any given application.

**Input Bias Currents**

Another non-ideal characteristic of op-amps results from the presence of small input bias currents at the inverting and non-inverting terminals. Once again, these are due to the internal construction of the input stage of an operational amplifier. **Figure 3** illustrates the presence of nonzero input bias currents IB going into an op-amp.

**Figure 3**

Typical values of I_{B+} and I_{B–} depend on the semiconductor technology employed in the construction of the op-amp. Op-amps with **bipolar transistor** input stages may see input bias currents as large as 1 μA, while for **FET input devices**, the input bias currents are less than 1 nA. These currents depend on the internal design of the op-amp and are not necessarily equal.

\[{{I}_{OS}}={{I}_{B+}}-{{I}_{B-}}\begin{matrix}{} & {} & (4) \\\end{matrix}\]

The latter parameter is sometimes more convenient from the standpoint of analysis.

**Output Offset Adjustment**

Both the offset voltage and the input offset current contribute to an output offset voltage V_{o, os}. Some op-amps provide a means for minimizing V_{o, os}. For example, the μA741 op-amp provides a connection for this procedure.

**Figure 4** shows a typical pin configuration for an op-amp in an eight-pin dual-in-line package (DIP) and the circuit used for nulling the output offset voltage. The variable resistor is adjusted until v_{out} reaches a minimum (ideally, 0 V). Nulling the output voltage in this manner removes the effect of both input offset voltage and current on the output.

**Figure 4 **Output offset voltage adjustment

**Slew Rate Limit**

Another important restriction in the performance of a practical op-amp is associated with rapid changes in voltage. The op-amp can produce only a finite rate of change at its output. This limit rate is called the **slew rate**.

Consider an ideal step input, where at t = 0 the input voltage is switched from 0 to V volts. Then we would expect the output to switch from 0 to AV volts, where A is the amplifier gain. However, vo can change at only a finite rate; thus,

\[{{\left| \frac{d{{v}_{0}}}{{{d}_{t}}} \right|}_{\max }}={{S}_{0}}\begin{matrix}{} & Slew\text{ }rate\text{ }limitation & (5) \\\end{matrix}\]

**Figure 5** shows the response of an op-amp to an ideal step change in input voltage. Here, S_{0}, the slope of v_{o}, represents the slew rate.

**Figure 5 **Slew rate limit in op-amps

The slew rate limitation can affect sinusoidal signals, as well as signals that display abrupt changes, as does the step voltage of **Figure 6.** This may not be obvious until we examine the sinusoidal response more closely.

It should be apparent that the maximum rate of change for a sinusoid occurs at the zero crossing, as shown by **Figure 7**. To evaluate the slope of the waveform at the zero crossing, let

\[\begin{matrix}{{v}_{in}}(t)=V\sin \omega t & such\text{ }that & {{v}_{0}}(t)=AV\sin \omega t & (6) \\\end{matrix}\]

**Figure 7 **The maximum slope of a sinusoidal signal varies with the signal frequency.

Then:

\[\frac{d{{v}_{0}}}{dt}=\omega AV\cos \omega t\begin{matrix}{} & {} & (7) \\\end{matrix}\]

The maximum slope of the sinusoidal signal will therefore occur at *ωt* = 0, *π*, 2*π, . . .,* so that

\[{{\left| \frac{d{{v}_{0}}}{{{d}_{t}}} \right|}_{\max }}=\omega AV={{S}_{0}}\begin{matrix}{} & {} & (8) \\\end{matrix}\]

Thus, the maximum slope of a sinusoid is proportional to both the signal frequency and the amplitude. The curve shown by a dashed line in **Figure 7** should indicate that as ω increases, so does the slope of v(t) at the zero crossings. What is the direct consequence of this result, then?

**Short-Circuit Output Current**

Recall the model for the op-amp shown in **Figure 3**, which depicted the internal circuit of the op-amp as an equivalent input impedance R_{in} and a controlled voltage source Av_{in}.

**Figure 7a:** Simple voltage amplifier model

In practice, the internal source is not ideal because it cannot provide an infinite amount of current (to the load, to the feedback connection, or to both). The immediate consequence of this non-ideal op-amp characteristic is that the maximum output current of the amplifier is limited by the so-called short-circuit output current I_{SC}:

\[\left| {{i}_{out}} \right|<{{I}_{SC}}\begin{matrix}{} & Short-circuit\text{ }output\text{ }current\text{ }limitation & (9) \\\end{matrix}\]

To further explain this point, consider that the op-amp needs to provide current to the feedback path (in order to “zero” the voltage differential at the input) and to whatever load resistance, R_{o}, may be connected to the output. **Figure 8** illustrates this idea for the case of an inverting amplifier, where *I*_{SC} is the load current that would be provided to a short-circuit load (*R _{o}* = 0).

**Figure 8**

**Common-Mode Rejection Ratio (CMRR)**

The CMRR is an amplifier characteristic that can be found in the data sheet for any particular amplifier, such as a **741 operational amplifier**.

$\begin{matrix}CMMR=20\log \left| \frac{{{A}_{DM}}}{{{A}_{CM}}} \right| & {} & in\text{ }dB \\\end{matrix}$

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]]>Op-amps are found in most measurement and instrumentation applications, serving as a versatile building block for many applications.

The behavior of an op-amp is well described by fairly simple models, which permit an understanding of its effects and applications without delving into its internal details. Its simplicity and versatility make the op-amp an appealing electronic device with which to begin understanding electronics and integrated circuits.

The lower right portion of **Figure 1** shows a standard single op-amp IC chip pin layout. It has two **input pins (2 and 3)** and one **output pin (6)**. Also notice the two **DC power supply pins (4 and 7)** that provide external power to the chip and thus *enable* the op-amp. Operational amplifiers are *active* devices; that is, they need an external power source to function. **Pin 4** is held at a low DC voltage $V_{S}^{-}$, while **pin 7** is held at a high DC voltage $V_{S}^{+}$. These two DC voltages are well below and above, respectively, the op-amp’s reference voltage and bound the output of the op-amp.

**Figure 1**(a) Small-signal op-amp model; (b) simplified op-amp circuit symbol; (c) generic op-amp IC schematic; (d) single op-amp IC chip pin layout.

The upper left portion of **Figure 1** shows the so-called small-signal, low-frequency model of an op-amp. For this model, the input impedance is R_{in} and the output impedance is R_{out}. The op-amp itself is a differential amplifier because its output is a function of the difference between two input voltages, v^{+} and v^{–}, which are known as the **non-inverting and inverting inputs**, respectively.

Notice that the value of the internal dependent voltage source is A (v^{+} − v^{–}), where A is the open-loop gain of the op-amp. In a practical op-amp, A is quite large by design, typically on the order of 10^{5} to 10^{7}. This large open-loop gain can be exchanged, by design, for a smaller closed-loop gain G to acquire various beneficial characteristics for an amplifier circuit, of which the op-amp is just one component.

**Practical op-amps** have a large open-loop gain A, as noted above. The input impedance R_{in} is also large, typically on the order of 10^{6} to 10^{12} Ω, while the output impedance R_{out} is small, typically on the order of 10^{0} or 10^{1} Ω.

In the **ideal case**, the open-loop gain and the input impedance would be infinite, while the output impedance would be zero. When the output impedance is zero, the output voltage of an ideal op-amp is simply:

\[{{v}_{out}}=A({{v}^{+}}-{{v}^{-}})=A\Delta v\begin{matrix}{} & {} & (1) \\\end{matrix}\]

But is this relationship practical when the open-loop gain A approaches infinity? The implication for a practical op-amp is that one of the **two following possibilities** will hold:

- In the case that Δv ≠ 0, the output voltage saturates near either the positive or negative DC power supply value, $V_{S}^{+}$or$V_{S}^{-}$, as shown in
**Figure 2.**These external DC power supply rails enable a practical op-amp to function but also bound the op-amp output voltage v_{out}. This case applies to all practical applications of an op-amp used in open-loop mode; that is, when there is no feedback from v_{out}to v^{–}.

**Figure 2 **Ideal operational amplifier

- In the case that Δv = 0, the output voltage is not determined by the op-amp itself but by whatever other circuitry is attached to it. When Aβ ≫ 1 the closed-loop gain of an amplifier is approximately equal to 1/β and largely independent of A itself. Thus, this case applies to all practical applications of an op-amp in closed-loop mode; that is, when negative feedback is present from v
_{out}to v^{–}.

Notice in **Figure 2** that the letter “A” does not appear within the triangle symbol, thus implying that the open-loop gain is infinite. Also implied by the ideal op-amp symbol is that the current into or out of either input terminal is zero. This result is a consequence of the infinite input impedance of an ideal op-amp and is known as the first golden rule of ideal op-amps:

\[\begin{matrix}{{i}^{+}}={{i}^{-}}=0 & First\text{ }golden\text{ }rule & (2) \\\end{matrix}\]

When Aβ ≫ 1 the difference between the two amplifier inputs, us and u_{f}, approaches zero. In the context of ideal op-amps, where A → ∞, the difference between the two amplifier inputs, v^{+} and v^{–}, will be zero exactly as long as there is a feedback path from v_{out} to v^{–}.

\[\begin{matrix}{{v}^{+}}={{v}^{-}} & \text{Second golden }rule;negative\text{ }feedback\text{ }required & (3) \\\end{matrix}\]

The **Golden Rules of Ideal Op-Amps**:

i^{+} = i^{–} = 0.

v^{+} = v^{–} (when negative feedback is present).

There are **three fundamental amplifiers** that utilize the operational amplifier and employ negative feedback. They are:

- The inverting amplifier.
- The non-inverting amplifier.
- The isolation buffer (or voltage follower).

These archetypes have many important applications and are the building blocks for other important amplifiers.

Understanding and recognizing these archetypes is an essential first step in the study of amplifiers based upon the op-amp. It is worth emphasizing that the op-amp is rarely used as a stand-alone amplifier; rather it is used along with other components to form specialized amplifiers.

**Figure 3** shows a basic inverting amplifier circuit. The name derives from the fact that the input signal v_{S} “sees” the inverting terminal (−) and that, as is shown below, the output signal v_{o} is an inverted (negative) version of the input signal.

The goal of the following analysis is to determine the relationship between the output and the input signals. To begin, assume the op-amp is ideal and apply KCL at the inverting node marked v^{–}.

\[{{i}_{S}}={{i}_{F}}+{{i}_{in}}\begin{matrix}{} & {} & (4) \\\end{matrix}\]

**Figure 3 **Inverting amplifier

However, the first golden rule of ideal op-amps states that i_{in} = i^{–} = 0. Thus, i_{S} = i_{F} such that R_{S} and R_{F} form a virtual series connection. Ohm’s law can be applied to each resistor to yield:

\[{{i}_{S}}=\frac{{{v}_{S}}-{{v}^{-}}}{{{R}_{S}}}\begin{matrix}{} & \begin{matrix}{{i}_{F}}=\frac{{{v}^{-}}-{{v}_{0}}}{{{R}_{F}}} & {} & {} \\\end{matrix} & (5) \\\end{matrix}\]

These expressions can be simplified by noting that v^{+} = 0 and then applying the second golden rule of ideal op-amps to realize v^{–} = v^{+} = 0. Thus:

\[\begin{matrix}\begin{align}& {{i}_{S}}={{i}_{F}} \\& or \\& \frac{{{v}_{S}}}{{{R}_{S}}}=\frac{-{{v}_{0}}}{{{R}_{F}}} \\\end{align} & {} & \left( 6 \right) \\\end{matrix}\]

Cross-multiply to find the closed-loop gain G:

\[\begin{matrix}G=\frac{{{v}_{0}}}{{{v}_{S}}}=-\frac{{{R}_{F}}}{{{R}_{S}}} & Inverting\text{ }Amplifier & (7) \\\end{matrix}\]

Note that the magnitude of G can be greater or less than 1.

An alternate approach is to apply voltage division across the virtual series connection of R_{S} and R_{F}.

\[\begin{matrix}\begin{align}& \frac{{{v}_{S}}-{{v}_{0}}}{{{v}_{S}}-0}=-\frac{{{R}_{S}}+{{R}_{F}}}{{{R}_{S}}} \\& or \\& 1-\frac{{{v}_{0}}}{{{v}_{S}}}=1+\frac{{{R}_{F}}}{{{R}_{S}}} \\\end{align} & {} & \left( 8 \right) \\\end{matrix}\]

Subtract 1 from each side of this expression to find the same result as **equation 7**.

Notice that the closed-loop gain G of an inverting amplifier is determined solely by the choice of resistors. This result was derived for an ideal op-amp.

For a practical op-amp the result is only slightly different as long as the open-loop gain A is large. It is important to remember that this result depends upon both golden rules of ideal op-amps and that, in particular, the second golden rule is valid only when negative feedback is present.

As long as the open-loop gain A is large, the presence of negative feedback from the output to the inverting input drives the voltage difference between the two input terminals to zero.

The input impedance of the inverting amplifier is simply:

\[{{R}_{in}}=\frac{{{v}_{in}}}{{{i}_{in}}}=\frac{{{v}_{S}}+0}{{{i}_{S}}}={{R}_{S}}\begin{matrix}{} & {} & (9) \\\end{matrix}\]

Notice the important role played by the virtual ground at the inverting terminal in making this calculation so easy. This result also reveals a shortcoming of the inverting amplifier. In general, an ideal amplifier would have an infinite input impedance so as to not load the source network. It is tempting to correct this problem by choosing R_{S} to be very large; however, in so doing, the closed-loop gain (**equation 7**) will be reduced. Thus, it is not possible to design an inverting amplifier to have a large gain and also a large input impedance. Alas, there is no such thing as a free lunch!

**Figure 4** shows a basic non-inverting amplifier circuit. The name derives from the fact that the input signal v_{S} “sees” the non-inverting terminal (+) and that, as is shown below, the output signal v_{o} is a non-inverted (positive) version of the input signal.

The goal of the following analysis is to determine the relationship between the output and the input signals. As was done for the inverting amplifier circuit, assume the op-amp is ideal and apply KCL at the inverting node marked v^{–}.

\[{{i}_{F}}={{i}_{1}}+{{i}_{in}}\begin{matrix}{} & {} & (10) \\\end{matrix}\]

**Figure 4 **Non-inverting amplifier

However, the first golden rule of ideal op-amps states that i_{in} = i^{–} = i^{+} = 0. Thus, i_{F} = i_{1} such that RF and R1 form a virtual series connection. Ohm’s law can be applied to each resistor to yield:

\[\begin{matrix}{{i}_{1}}=\frac{{{v}^{-}}-0}{{{R}_{1}}} & {} & {{i}_{F}}=\frac{{{v}_{out}}-{{v}^{-}}}{{{R}_{F}}} \\or & {} & (11) \\\frac{{{v}^{-}}}{{{R}_{1}}}=\frac{{{v}_{0}}-{{v}^{-}}}{{{R}_{F}}} & {} & {} \\\end{matrix}\]

Since there is negative feedback present, the second golden rule of ideal op-amps can be applied such that v^{–} = v^{+}. Notice that because i_{in} = 0, the voltage drop across R_{S} is zero with the result that v^{–} = v^{+} = v_{S}. Substitute this result into **equation 11** and rearrange terms to yield the **closed-loop gain G**:

\[\begin{matrix}G=\frac{{{V}_{0}}}{{{v}_{S}}}=1+\frac{{{R}_{F}}}{{{R}_{1}}} & Non-inverting\text{ }amplifier & (12) \\\end{matrix}\]

Note that G ≥ 1.

An alternate approach is to apply voltage division across the virtual series connection of R_{1} and R_{F}.

\[\frac{{{V}_{0}}-0}{{{v}^{-}}-0}=\frac{{{R}_{1}}+{{R}_{F}}}{{{R}_{1}}}\begin{matrix}{} & {} & (13) \\\end{matrix}\]

Since v^{–} = v_{S}:

\[\frac{{{V}_{0}}}{{{v}_{S}}}=1+\frac{{{R}_{F}}}{{{R}_{1}}}\begin{matrix}{} & {} & (14) \\\end{matrix}\]

Which is the same result as that found in **equation 12**.

Notice that the closed-loop gain G of a non-inverting amplifier is also determined solely by the choice of resistors. This result was derived for an ideal op-amp.

For a practical op-amp the result is only slightly different as long as the open-loop gain A is large. It is important to remember that this result depended upon both golden rules of ideal op-amps and that, in particular, the second golden rule is valid only when negative feedback is present.

As long as the open-loop gain A is large, the presence of negative feedback from the output to the inverting input drives the voltage difference between the two input terminals to zero.

The input impedance of the non-inverting amplifier is simply:

\[{{R}_{in}}=\frac{{{v}_{in}}}{{{i}_{in}}}=\frac{{{v}_{S}}-0}{{{i}_{in}}}\to \infty \begin{matrix}{} & {} & (15) \\\end{matrix}\]

In practice, the input impedance of a non-inverting amplifier is very large due to the very large input impedance of the op-amp, which limits i_{in} to very small values.

Notice that the closed-loop gain of the non-inverting amplifier is independent of its input impedance. Thus, the non-inverting amplifier does not suffer from a trade-off between gain and input impedance, as does the inverting amplifier.

However, the gain of a non-inverting amplifier is limited to values greater than one, whereas the gain of the inverting amplifier can take on any value.

**Figure 5** shows an isolation buffer, which is also known as a voltage follower. Notice that the input signal v_{S} “sees” the non-inverting terminal (+) such that the output signal v_{o} should be a non-inverted (positive) version of v_{S}.

The analysis of this circuit is as simple as the circuit itself. Assume that the op-amp is ideal. Since negative feedback is present, both golden rules are valid. That is:

\[{{i}^{+}}={{i}^{-}}=0\begin{matrix}{} & and\begin{matrix}{} & {{v}^{+}}={{v}^{-}}\begin{matrix}{} & {} & (16) \\\end{matrix} \\\end{matrix} \\\end{matrix}\]

**Figure 5 **Isolation Buffer or Voltage Follower

By observation, v^{+} = v_{S} and v^{–} = v_{out} with the result that the closed-loop gain G is:

\[G=\frac{{{v}_{0}}}{{{v}_{S}}}=1\begin{matrix}{} & Isolation\text{ }Buffer & (17) \\\end{matrix}\]

The reason this circuit is called a **voltage follower** should now be obvious; the output voltage v_{o} “follows” (equals) the input voltage v_{S}. On the other hand, the reason this circuit is also known as an isolation buffer is not obvious. However, since i^{+} = 0, the ideal op-amp is said to possess an infinite input resistance or input impedance such that the voltage source experiences no loading from the op-amp. Yet the circuit still reproduces v_{S} at the output.

Any loading effects at the output are experienced by the op-amp rather than the voltage source, such that the source is isolated or buffered from the output.

The input impedance of an isolation buffer is simply:

\[{{R}_{in}}=\frac{{{v}_{in}}}{{{i}_{in}}}=\frac{{{v}_{S}}-0}{{{i}_{in}}}\to \infty \begin{matrix}{} & {} & (18) \\\end{matrix}\]

In practice, the input impedance of an isolation buffer is very large due to the very large input impedance of the op-amp, which limits i_{in} to very small values. The closed-loop gain is fixed at unity as long as the open-loop gain A is large such that v^{–} will be driven to v^{+} by negative feedback.

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]]>The post Enhancement Mode MOSFET appeared first on Electrical A2Z.

]]>

**Figure 1 **The *n*-channel enhancement MOSFET construction and circuit symbol

Consider the case when the gate and source terminals are connected to a reference node and the drain terminal is connected to a positive voltage supply *V _{DD}*, as shown in

Likewise, the voltage across the *pn*^{+} junction between the bulk and the source is zero, and thus that junction is also reverse-biased. Thus, a path between drain and source consists of two reverse-biased *pn*^{+} junctions such that the current from drain to source is effectively zero. In this case, the resistance from drain to source is on the order of 10^{12} Ω.

When the voltage from gate to source is zero, the *n*-channel enhancement-mode MOSFET acts as an open-circuit. Thus, enhancement-mode devices are referred to as *normally off* and their channels as *normally open.*

Suppose now that a positive DC voltage *V _{GG}* is applied to the gate as shown in

The term ** enhancement mode** refers to the influence of the gate voltage in enhancing the conductivity of the channel. The term

**Figure 2 **Channel formation in NMOS transistor: (a) With zero gate voltage, the source-bulk and bulk-drain junctions are both reverse-biased, and the channel acts as an open-circuit; (b) when a positive gate voltage is applied, positive majority carriers in the bulk (i.e., holes) are repelled by the gate leaving behind negatively charged atoms. Also, negative majority carriers from the source and drain (i.e., electrons) are drawn toward the gate. The result is a conducting *n*-type channel between the source and drain regions.

** Depletion-mode** devices also exist, in which an externally applied field depletes the channel of charge carriers by reducing the effective channel width. Depletion-mode MOSFETs are normally on (i.e., the channel is conducting) and are turned off (i.e., the channel is not conducting) by an external gate voltage.

Both enhancement- and depletion-mode MOSFETs are available with either *n*– or *p*-type channels. Enhancement-mode devices do not have a conducting channel built in; however, one can be created by the *action* of the gate.

On the other hand, depletion-mode devices do have a built-in conducting channel that can be depleted by the *action* of the gate. Depending upon the mode and channel type, FETs can be *active high* or *active low* devices, where *high* and *low* refer to the voltage of the gate relative to a common reference.

**Table 1** summarizes these results. *n*– and *p*-channel MOSFETs are referred to as **NMOS** and **PMOS** transistors, respectively.

**Table 1**

**Operating Regions and the Threshold Voltage V_{t}**

When the gate-to-bulk voltage of an NMOS transistor (See **Figure 3**) is less than a threshold voltage *V _{t}*, a channel will not form between the source and drain. The result is that no current can be conducted from drain to source and the transistor is in the

**Figure 3 **Regions of operation of NMOS transistor

When the gate-to-bulk voltage is greater than the threshold voltage *V _{t}* at any point between the source and drain, a conducting

If the drain is also connected to the **same common reference** such that *v _{DS}* = 0, then a channel of uniform thickness will be formed from drain to source when

Note that if *v _{DS}* = 0, then ${{v}_{GD}}\equiv {{v}_{GS}}-{{v}_{DS}}={{v}_{GS}}$, the channel has a uniform thickness, and its resistance per unit channel length is also uniform. In this state, known as the

**In other words**, for a given value of *v _{GS}*, the channel current

\[\begin{matrix}{{i}_{D}}\propto {{v}_{DS}} & when & \begin{matrix}{{v}_{DS}}\ll {{v}_{OV}} & \text{Ohmic Region} & (1) \\\end{matrix} \\\end{matrix}\]

When *v _{GS}* >

**In addition**, as long as *v _{GD}* >

\[\begin{matrix}\begin{matrix}{{i}_{D}}\propto {{v}^{2}}_{DS} & when & {{v}_{DS}}<{{v}_{OV}} \\\end{matrix} & \text{Triode Region} & \left( 2 \right) \\\end{matrix}\]

It is important to realize that the ohmic region is simply one part of the triode region when *v _{DS}* «

Eventually, if *v _{DS}* is continually increased, it will exceed

**However**, any increase in *v _{DS}* beyond

\[\begin{matrix}\begin{matrix}{{i}_{D}}\propto {{v}^{2}}_{OS} & when & {{v}_{DS}}>{{v}_{OV}} \\\end{matrix} & \text{Saturation Region} & (3) \\\end{matrix}\]

These operating regions and their dependence upon *v _{GD}* and

**Channel Current i_{D} and the Conductance Parameter K**

The ability of the channel to conduct is dependent on various mechanisms, the effects of which are captured in a conductance parameter *K*, defined as:

\[K=\frac{W}{L}\frac{\mu {{C}_{ox}}}{2}\begin{matrix}{} & {} & (4) \\\end{matrix}\]

Where *W* is the cross-sectional width of the channel, *L* is the channel length, *μ* is the mobility of the majority channel charge carrier (electrons in *n*-channel devices, holes in *p*-channel devices), and *C*_{ox} is the gate-channel capacitance due to the thin insulating oxide layer. The units of *K* are A/V^{2}.

With this definition of the conductance parameter, the relationship between *i _{D}* and

\[\begin{matrix}\begin{matrix}{{i}_{D}}=0 & when & {{v}_{GS}}\ll V \\\end{matrix} & \text{Cutoff Region} & (5) \\\end{matrix}\]

In the **triode region**:

\[\begin{matrix}\begin{matrix}{{i}_{D}}=K(2{{v}_{OV}}-{{v}_{DS}}){{v}_{DS}} & when & {{v}_{DS}}<{{v}_{OV}} \\\end{matrix} & \text{Triode Region} & (6) \\\end{matrix}\]

When *v _{DS }*<<

\[\begin{matrix}\begin{matrix}{{i}_{D}}\approx 2K{{v}_{OV}}{{v}_{DS}} & when & {{v}_{DS}}\ll {{v}_{OV}} \\\end{matrix} & \text{Ohmic Region} & (7) \\\end{matrix}\]

Which is the linear relationship characteristic of the ohmic region. In the ohmic region, the transistor acts as a voltage-controlled resistor. This property allows transistors to act as resistors in **integrated circuit (IC) designs**. Other applications of a voltage-controlled resistor are found in tunable (variable-gain) amplifiers and in analog gates.

In the **saturation region**:

\[\begin{matrix}\begin{matrix}{{i}_{D}}\approx Kv_{OV}^{2} & when & {{v}_{DS}}>{{v}_{OV}} \\\end{matrix} & \text{Saturation Region} & (8) \\\end{matrix}\]

This relationship is only approximate. This relationship is made more exact by accounting for the **Early effect**, which describes the effect of *v _{DS}* on the effective length of the channel. This effect is accounted for by incorporating the

\[\begin{matrix}\begin{matrix}{{i}_{D}}=Kv_{OV}^{2}\left( 1+\frac{{{v}_{DS}}}{{{V}_{A}}} \right) & when & {{v}_{DS}}>{{v}_{OV}} \\\end{matrix} & \text{Saturation Region} & (9) \\\end{matrix}\]

When *V _{A}* is large compared to

The **three regions of operation** can also be identified in the characteristic curves shown in **Figure 4**, which can be generated from the circuit of **Figure 2(b)** by varying the gate and drain voltages relative to the source voltage.

Notice that for *v _{GS}* <

In the **saturation region**, the transistor drain current is nearly constant and independent of *v _{DS}*. In fact, its value is proportional to $v_{GS}^{2}$.

Finally, in the **triode region**, the drain current is strongly dependent on *v _{GS}* and

**Figure 4 **Characteristic drain curves for an NMOS transistor with *V _{t}* = 2 V and

**Operation of the P-channel Enhancement-Mode MOSFET**

The operation of a PMOS enhancement-mode transistor is very similar in concept to that of an NMOS device. **Figure 5** depicts a test circuit and a sketch of the device construction.

Note that the roles of the *n*-type and *p*-type materials are reversed and that the charge carriers in the channel are holes, not electrons. Further, the threshold voltage *V _{t}* is now negative. However, if

In particular, **Figure 6** depicts the behavior of a PMOS transistor in terms of the gate-to-drain and gate-to-source voltages, in analogy with **Figure 3**. The **resulting equations for the three modes of operation of the PMOS transistor** are summarized below:

**Cutoff region**: when v_{SG} < |V_{t} | and v_{DG} < |V_{t} |.

\[{{i}_{D}}=0\begin{matrix}{} & Cutoff\text{ }region & (10) \\\end{matrix}\]

**Saturation region**: when v_{SG} > |V_{t} | and v_{DG} < |V_{t} |.

\[{{i}_{D}}\cong K{{\left( {{v}_{SG}}-\left| {{V}_{t}} \right| \right)}^{2}}\begin{matrix}{} & Saturation\text{ }region & (11) \\\end{matrix}\]

**Triode region**: when v_{SG} >|V_{t}| and v_{DG} >|V_{t}|.

\[{{i}_{D}}=K\left[ 2{{\left( {{v}_{SG}}-\left| {{V}_{t}} \right| \right)}^{2}}{{v}_{SD}}-v_{SD}^{2} \right]\begin{matrix}{} & Triode\text{ }or\text{ }ohmic\text{ }region & (12) \\\end{matrix}\]

**Figure 5 **The *p*-channel enhancement-mode field-effect transistor (PMOS)

**Figure 6 **Regions of operation of PMOS transistor

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]]>The post Bipolar Junction Transistor (BJT) Theory appeared first on Electrical A2Z.

]]>The Bipolar Junction Transistor (BJT) counterpart to the NPN is the PNP transistor, which utilizes the same doping scheme except that the n and p regions are swapped with respect to the NPN. In both of these BJT types, the heavily doped emitter region is often labeled n^{+} or p^{+} to distinguish it from the lightly doped collector.

**Figure 1** illustrates the construction, symbols, and nomenclature for the two types of Bipolar Junction Transistor (BJTs). Notice that there are the two PN junctions in a BJT: the **emitter-base junction** (EBJ) and the **collector-base junction** (CBJ). The operating mode of a BJT depends upon whether these junctions are reverse- or forward-biased, as indicated in **Table 1.**

**Figure 1 **Bipolar junction transistors (BJT)

**Table 1 BJT operating modes**

Mode |
EBJ |
CBJ |
Application |

Cutoff | Reverse-biased | Reverse-biased | Open switch |

Active | Forward-biased | Reverse-biased | Amplifier |

Saturation | Forward-biased | Forward-biased | Closed switch |

Although the construction of a Bipolar Junction Transistor (BJT) results in two opposing PN junctions, it is important to avoid modeling a BJT as two identical but opposing diodes. The EBJ always behaves as a true diode; however, because of the thin base region and the lightly doped collector region, the CBJ does not.

**Figure 2** depicts the basic geometry of a cross section of a Bipolar Junction Transistor (BJT). The base region is shown much thicker (compared to the emitter and collector) for the sake of clarity. There are two key points to note from the **figure:** (1) the base is a very thin envelope around the emitter, and (2) the collector is much larger than the emitter and the base because it envelopes both and is itself relatively thick compared to the emitter. The result of this geometry is that the collector can receive large numbers of mobile charge carriers without any significant impact upon its density of charge carriers.

**Figure 2 **Cross section of an NPN transistor. Notice that the collector is much larger and much more lightly doped than the emitter. However, the base is, in fact, very thin compared to the emitter and collector.

When both PN junctions are reverse-biased, no current is present across either junction and the path from collector to emitter can be approximated as an open-circuit. In fact, small reverse currents due to minority carriers are present across the junctions, but for most practical applications these reverse currents are negligible.

In silicon-based Bipolar Junction Transistor (BJTs), the offset voltage for the EBJ is the same 0.6 V presented in Chapter 9 for single silicon diodes. Thus, in cutoff mode, when v_{BE} < 0.6 V, the transistor acts as a switch in its off (open-circuit) condition.

**Figure 3** shows a **Norton source** connected across the base and emitter terminals of an NPN transistor and the resulting i-v characteristic of its EBJ. Notice that i_{B} ≈ 0 when v_{BE} ≤ 0.6 V, which is cutoff mode. However, when the EBJ is forward-biased such that v_{BE} ≥ 0.6 V, current is conducted as in a typical diode.

Majority carriers in the emitter and base drift across the EBJ under the influence of the forward-bias voltage in excess of the potential barrier of the depletion region. However, since the emitter is heavily doped while the base is lightly doped, the current I_{E} across the EBJ is dominated by the majority carriers from the emitter.

**Figure 3 **The i-v characteristic of the emitter-base junction of a typical NPN transistor

The i-v characteristics of the EBJ for NPN and PNP transistors are identical except that the abscissas are v_{BE} and v_{EB}, respectively.

The discussion below is based upon the behavior of an NPN transistor; however, the behavior of a PNP transistor is completely analogous to that of an NPN transistor, except that positive and negative charge carriers are interchanged and the EBJ is forward-biased from emitter to base rather than from base to emitter.

The behavior of a PNP transistor is completely analogous to that of an NPN transistor, except that positive and negative charge carriers are interchanged and the EBJ is forward-biased from emitter to base rather than from base to emitter.

For an NPN Bipolar Junction Transistor (BJT), the majority carriers in the emitter are electrons while the majority carriers in the base are holes, as indicated in **Figure 4.** Some of these electrons recombine with holes in the base; however, since the base is lightly doped, most of these electrons remain mobile minority carriers in the p-type base. As these mobile electrons cross the EBJ, their growing concentration in the base causes them to diffuse toward the CBJ. The equilibrium concentration of these mobile electrons throughout the base region is a maximum at the EBJ and is given by:

\[{{({{n}_{p}})}_{\max }}={{({{n}_{p}})}_{o}}({{e}^{{{v}_{BE}}/{{V}_{T}}}}-1)\begin{matrix}{} & {} & (1) \\\end{matrix}\]

**Figure 4 **Flow of emitter electrons into the collector in an NPN transistor

Where v_{BE} is the forward-bias voltage from base to emitter and (n_{p})_{o} is the thermal equilibrium concentration of electrons in the base. Since the base is very thin, the equilibrium concentration gradient across the base is nearly linear, as depicted in **Figure 5,** such that the electron diffusion rate from the EBJ to the CBJ can be approximated as:

\[\frac{A{{q}_{e}}{{D}_{n}}{{({{n}_{p}})}_{\max }}}{W}\begin{matrix}{} & {} & (2) \\\end{matrix}\]

**Figure 5 **Equilibrium concentration gradient of free electrons in the p-type base of a forward-biased NPN transistor.

Where A is the cross-sectional area of the EBJ, W is the width of the base (not including the width of the two bounding depletion regions), and D_{n} is the diffusivity of electrons in the base.

It is important to note that this electron diffusion rate is temperature dependent and that it represents a diffusion current directed from the CBJ to the EBJ because of the convention that the direction of positive current is the direction of flow of positive charge carriers. Once these diffusing electrons reach the CBJ they are swept into the collector by the reverse-bias voltage across the CBJ. Thus, the **collector current** i_{C} is:

\[\begin{matrix}{{i}_{C}}=\frac{A{{q}_{e}}{{D}_{n}}{{({{n}_{p}})}_{0}}}{W}({{e}^{{{v}_{BE}}//{{V}_{T}}}}-1) & {} & {} \\=\frac{A{{q}_{e}}{{D}_{n}}{{n}^{2}}_{i}}{W{{N}_{A}}}({{e}^{{{v}_{BE}}//{{V}_{T}}}}-1) & {} & (3) \\={{I}_{S}}({{e}^{{{v}_{BE}}//{{V}_{T}}}}-1) & {} & {} \\\end{matrix}\]

Where N_{A} is the doping concentration of holes in the base and I_{S} is known as the **scale current** because it scales with the cross-sectional area A of the EBJ. Typical values of I_{S} range from 10^{−12} A to 10^{−15} A.

The **base current** i_{B} (from base to emitter) is comprised of those majority carriers in the base (e.g., holes for an NPN transistor) that traverse the EBJ. Some of these carriers recombine with the majority carriers in the emitter (e.g., electrons for an NPN transistor); however, those majority carriers lost to recombination are replaced by additional majority carriers supplied by V_{1}. Because the concentration of these majority carriers is proportional to ${{e}^{{}^{{{v}_{BE}}}/{}_{{{V}_{T}}}}}-1$, the base current is proportional to the collector current i_{C} such that:

\[{{i}_{B}}=\frac{{{i}_{C}}}{\beta }=\frac{{{i}_{C}}}{{{h}_{FE}}}\begin{matrix}{} & {} & (4) \\\end{matrix}\]

Where β is known as the forward **common-emitter current gain** with typical values ranging from 20 to 200. Although β can vary significantly from one transistor to another, most practical electronic devices only require that β>> 1.

**Figure 6** depicts the flow of charge carriers from emitter to base to collector and from base to emitter, as discussed above, for an NPN transistor. A Bipolar Junction Transistor (BJT) is a bipolar device because its current is comprised of both electrons and holes.

The parameter β is not often found in a data sheet. Instead, the forward **DC** value of β is listed as h_{FE}, which is the **large-signal current gain.** A related parameter, h_{fe}, is the **small-signal current gain.**

Finally, to satisfy KCL, the **emitter current** i_{E} must be the sum of the collector and base currents and, therefore, must also be proportional to${{e}^{{}^{{{v}_{BE}}}/{}_{{{V}_{T}}}}}$. Thus:

\[\begin{matrix}\begin{align}& {{i}_{E}}={{I}_{ES}}({{e}^{{{v}_{BE}}//{{V}_{T}}}}-1) \\& ={{i}_{C}}+{{i}_{B}}=\frac{\beta +1}{\beta }{{i}_{C}}=\frac{{{i}_{C}}}{\alpha } \\\end{align} & {} & (5) \\\end{matrix}\]

Where I_{ES} is the reverse **saturation current** and α is the **common-base current gain** with a typical value close to, but not exceeding, 1.

A Bipolar Junction Transistor (BJT) remains in active mode as long as the CBJ is reverse-biased; that is, as long as V_{2} > 0, electrons diffusing across the base will be swept away into the collector once they reach the CBJ. However, when the CBJ is forward-biased (V_{2} < 0), these diffusing electrons are no longer swept away into the collector but instead accumulate at the CBJ such that the concentration of minority carrier electrons there is no longer zero.

The magnitude of **this concentration** increases as V_{2} decreases, such that the concentration gradient across the base decreases. The result is that the diffusion of minority carrier electrons across the base decreases; in other words, the collector current i_{C} decreases as the forward bias of the CBJ increases.

It is important to realize that as the concentration gradient across the base decreases and the rate of diffusion across the base decreases, the rate of increase of the concentration near the CBJ slows and the concentration gradient across the base approaches zero asymptotically. This asymptotic process expresses itself as an upper limit on the forward-bias voltage across the CBJ.

**Figure 7** defines **three voltages** across the terminals of an NPN transistor. In saturation, the action of the transistor limits v_{CB} such that v_{CE} is always positive, although small, with a typical value of 0.2 V.

In fact, saturation mode is often best determined by the value of v_{CE}, which has a value of approximately 0.2 V for a silicon-based Bipolar Junction Transistor (BJT).

**Figure 7 **Definition of Bipolar Junction Transistor (BJT) voltages and currents

In saturation, the collector current is no longer proportional to the base current and the collector-emitter voltage V_{CE} for a silicon-based BJT is small (< 0.4 V). An increasing base current drives a BJT further into saturation, and V_{CE} approaches the saturation limit of V_{CEsat} ≈ 0.2 V.

\[{{V}_{CEsat}}\approx 0.2V\begin{matrix}{} & \text{Saturation limit}\begin{matrix}{} & {} & (6) \\\end{matrix} \\\end{matrix}\]

The voltages and currents shown in Figure 9 for an NPN transistor are related by KCL and KVL.

\[{{v}_{CE}}={{v}_{CB}}+{{v}_{BE}}\begin{matrix}{} & KVL\begin{matrix}{} & {} & (7) \\\end{matrix} \\\end{matrix}\]\[{{i}_{E}}={{i}_{C}}+{{i}_{B}}\begin{matrix}{} & KCL\begin{matrix}{} & {} & (8) \\\end{matrix} \\\end{matrix}\]

The Bipolar Junction Transistor (BJT) currents are temperature dependent because they are proportional to both $n_{i}^{2}$ and${{e}^{{}^{{{v}_{BE}}}/{}_{{{V}_{T}}}}}$. These currents are also proportional to the cross-sectional area A of the EBJ and inversely proportional to the effective width W of the base.

The relationships between these voltages and currents are commonly represented by a graph of i_{C} versus v_{CE}, with i_{B }treated as a parameter. A typical example of such a graph is shown in **Figure 8.** The operating mode of a BJT is completely specified by these three variables. The three modes of operation are indicated in the figure. Cutoff and saturation modes occur when i_{c} and v_{CE} are very small, respectively.

**Figure 8 **Typical characteristic lines of a Bipolar Junction Transistor (BJT)

For any fixed value of i_{B}, the slope of the transistor characteristic is very small in active mode. In the ideal case, this slope would be zero; however, the effective width of the base decreases with v_{CE} such that the concentration gradient of charge carriers in the base increases and, thus, the collector current increases as well. This increase in i_{C} with v_{CE} is known as the **Early effect** or **base-width modulation.**

It is important to realize that the operating values of i_{B}, i_{C}, and v_{CE}, and the operating mode itself, are determined by the external circuitry attached to the Bipolar Junction Transistor (BJT).

It is essential to keep in mind the key characteristics of the cutoff, active, and saturation modes, which are the same for both NPN and PNP transistors, and which are summarized in the **box below**.

**Cutoff mode:** Both the EBJ and CBJ are reverse-biased such that all three currents i_{C}, i_{B}, and i_{E} are approximately zero. In cutoff mode, a BJT acts as an open switch between the collector and emitter.

**Active mode:** The EBJ is forward-biased while the CBJ is reverse-biased. The Bipolar Junction Transistor (BJT) currents are related by:

In active mode, these currents are largely independent of v_{CB} and the BJT acts as a linear amplifier.

**Saturation mode:** Both the EBJ and CBJ are forward-biased such that v_{BE} ≈ 0.7 V and v_{CE}≈ 0.2 V. The collector current i_{C} is highly sensitive to small changes in v_{CE}, and, since v_{CE} is small, i_{C} is largely determined by external circuitry attached to the collector terminal. In saturation mode, the BJT approximates a closed switch between the collector and emitter.

A few simple voltage measurements permit a quick determination of the state of a transistor. Consider, for example, an NPN transistor placed in the circuit of **Figure 9,** where:

and

**Figure 9 **Determination of the operating mode of a Bipolar Junction Transistor (BJT)

Assume that the measured collector, emitter, and base terminal voltages are:

The method used in determining the state of a transistor is to assume an operating mode and then test the assumption against the known data. It is usually best to first assume cutoff mode and check whether the EBJ is reverse-biased. The voltage across the EBJ is:

Thus, the EBJ is forward-biased, not reverse-biased, and the transistor is not in cutoff mode.

One can next assume either active or saturation mode and test the assumption. For this example, assume saturation mode and test whether the CBJ is forward-biased. The voltage across the CBJ is:

Thus, the CBJ is reverse-biased and the transistor is in active mode. The same determination could be made by evaluating the voltage across the collector-emitter terminals.

The requirement for saturation mode is V_{CE} > 0.4 V, which is clearly not satisfied.

Since the transistor is in active mode, it is possible to calculate the common-emitter current gain β. The base current is:

The collector current is:

Thus, the current amplification factor is:

The operating point of the **transistor** in the given circuit can be located on a characteristic plot. It is important to note that the operating mode of the transistor is determined by the attached circuitry. In this example, the values of V_{B}, V_{C}, and V_{E} were measured. However, for analytic problems, these values can be calculated using **KCL**, **KVL**, **Ohm’s law**, and the known characteristics of the three possible modes of operation.

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]]>Further, while the power produced by a single-phase system has a pulsating nature a three-phase system can deliver a steady, constant supply of power. For example, later in this article it will be shown that a three-phase generator producing three **balanced voltages**—that is, voltages of equal amplitude and frequency displaced in phase by 120°—has the property of delivering constant instantaneous power.

The change to three-phase AC power systems from the early DC system proposed by Edison was due to a number of reasons: the efficiency resulting from transforming voltages up and down to minimize transmission losses over long distances, the ability to deliver constant power, a more efficient use of conductors, and the ability to provide starting torque for industrial motors.

Consider a three-phase source connected in a **wye (star) configuration,** as shown in **Figure 1**. Each of the three voltages is 120° out of phase with the others, such that:

**Figure 1 **Balanced three-phase AC circuit

\[\begin{matrix}\begin{align}& \overset{\text{ }\!\!\tilde{\ }\!\!\text{ }}{\mathop{{{\text{V}}_{\text{an}}}}}\,=\overset{\tilde{\ }}{\mathop{{{V}_{an}}}}\,\angle {{0}^{^{o}}} \\& \overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{bn}}}}}\,=\overset{\tilde{\ }}{\mathop{{{V}_{bn}}}}\,\angle -({{120}^{^{o}}}) \\& \overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{cn}}}}}\,=\overset{\tilde{\ }}{\mathop{{{V}_{cn}}}}\,\angle (-{{240}^{^{o}}})=\overset{\sim }{\mathop{{{V}_{cn}}}}\,\angle {{120}^{o}} \\\end{align} & {} & (1) \\\end{matrix}\]

If the three-phase source is balanced, then:

\[\overset{\text{ }\!\!\tilde{\ }\!\!\text{ }}{\mathop{{{\text{V}}_{\text{an}}}}}\,\text{+}\overset{\text{ }\!\!\tilde{\ }\!\!\text{ }}{\mathop{{{\text{V}}_{\text{bn}}}}}\,\text{+}\overset{\text{ }\!\!\tilde{\ }\!\!\text{ }}{\mathop{{{\text{V}}_{\text{cn}}}}}\,\text{=0}\begin{matrix}{} & Balanced\text{ }phase\text{ }voltages\begin{matrix}{} & {} & (2) \\\end{matrix} \\\end{matrix}\]

The result is the so-called **positive abc sequence,** as shown in **Figure 2.** In the wye (star) configuration, the three phase voltages share a common *neutral node,* denoted by *n.*

**Figure 2 **Positive, or abc, sequence for balanced three-phase voltages

It is also possible to define **line voltages** as the potential differences between lines aa′ and bb′, lines aa′ and cc′, and lines bb′ and cc’. Each **line voltage** is related to the phase voltages by:

\[\begin{matrix}\overset{\text{ }\!\!\tilde{\ }\!\!\text{ }}{\mathop{{{\text{V}}_{\text{ab}}}}}\,\text{=}\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{an}}}}}\,\text{-}\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{bn}}}}}\,\text{=}\sqrt{3}\overset{\tilde{\ }}{\mathop{V}}\,\angle {{30}^{o}} & {} & {} \\\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{bc}}}}}\,\text{=}\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{bn}}}}}\,\text{-}\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{cn}}}}}\,=\sqrt{3}\overset{\tilde{\ }}{\mathop{V}}\,\angle (-{{90}^{o}}) & {} & (4) \\\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{ca}}}}}\,\text{=}\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{cn}}}}}\,\text{-}\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{an}}}}}\,=\sqrt{3}\overset{\tilde{\ }}{\mathop{V}}\,\angle {{150}^{o}} & {} & {} \\\end{matrix}\]

It is instructive to note that the circuit of **Figure 1** can be redrawn as shown in **Figure 3**, where it is clear that the three branches are in parallel.

**Figure 3 **Balanced three-phase AC circuit (redrawn)

When **Z**_{a} = **Z**_{b} = **Z**_{c} = **Z**, the wye (star) load configuration is also balanced. When both the source and load networks are balanced, KCL requires that the current **Ĩ**_{n} in the neutral line n − n′ be identically zero.

\[\overset{\tilde{\ }}{\mathop{{{\text{I}}_{\text{n}}}}}\,\text{=}\overset{\tilde{\ }}{\mathop{{{\text{I}}_{\text{a}}}}}\,\text{+}\overset{\tilde{\ }}{\mathop{{{\text{I}}_{\text{b}}}}}\,\text{+}\overset{\tilde{\ }}{\mathop{{{\text{I}}_{\text{c}}}}}\,\text{=}\frac{\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{an}}}}}\,\text{+}\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{bn}}}}}\,\text{+}\overset{\tilde{\ }}{\mathop{{{\text{V}}_{\text{cn}}}}}\,}{\text{ }\!\!Z\!\!\text{ }}\text{=0}\begin{matrix}{} & \text{(5)} \\\end{matrix}\]

Another important characteristic of a balanced three-phase power system is illustrated by a simplified version of **Figure 3**, where the balanced load impedances are replaced by three equal resistors R. Since 𝜃_{R} = 0, the instantaneous power p(t) delivered to each resistor is given by equation [with 𝜃_{V} = 𝜃_{I} and with the freely chosen reference (𝜃_{V})_{a} = 0)] to be:

\[\begin{matrix}{{p}_{a}}(t)=\frac{\overset{\tilde{\ }}{\mathop{{{V}^{2}}}}\,}{R}(1+\cos 2\omega t) & {} & {} \\{{p}_{b}}(t)=\frac{\overset{\tilde{\ }}{\mathop{{{V}^{2}}}}\,}{R}[(1+\cos (2\omega t-{{120}^{o}})] & {} & (6) \\{{p}_{c}}(t)=\frac{\overset{\tilde{\ }}{\mathop{{{V}^{2}}}}\,}{R}[(1+\cos (2\omega t-{{120}^{o}})] & {} & {} \\\end{matrix}\]

The total instantaneous power p(t) delivered to the total load is the sum:

\[\begin{matrix}p(t)={{p}_{a}}(t)+{{p}_{b}}(t)+{{p}_{c}}(t) & {} & {} \\=\frac{\overset{\tilde{\ }}{\mathop{{{V}^{2}}}}\,}{R}[(3+\cos 2\omega t+\cos (2\omega t-{{120}^{o}})+\cos (2\omega t+{{120}^{o}})] & {} & (7) \\=\frac{\overset{\tilde{\ }}{\mathop{3{{V}^{2}}}}\,}{R}=\text{constant!} & {} & {} \\\end{matrix}\]

It is worthwhile to verify that the sum of the three cosine terms is identically zero. (Hint: Consider the phasor sum of e^{j(2ωt)}, e^{j(2ωt–π/3)} and e^{j(2ωt+π/3)}.)

Thus, with the simplified balanced resistive load, the total power delivered to the load by the balanced three-phase source is constant. This is an extremely important result, for a very practical reason: Delivering power in a steady fashion (as opposed to the pulsating nature of single-phase power) reduces “wear and tear” on the source and load.

It is also possible to connect three AC sources in a **delta** (**Δ**) **configuration,** as shown in **Figure 4** although it is rarely used in practice.

**Figure 4 **Delta configuration

These results for purely resistive loads can be generalized for any arbitrary balanced complex load. Consider again in **Figure 5**, where now the balanced load consists of three complex impedances:

\[{{Z }_{a}}={{Z }_{b}}={{Z }_{c}}={{Z }_{y}}=\left| {{Z }_{y}} \right|\angle \theta \begin{matrix}{} & {} & (8) \\\end{matrix}\]

Because of the common neutral line n − n′, each impedance sees the corresponding phase voltage across itself. Therefore, since $\overset{\tilde{\ }}{\mathop{{{V}_{an}}}}\,=\overset{\tilde{\ }}{\mathop{{{V}_{bn}}}}\,=\overset{\tilde{\ }}{\mathop{{{V}_{cn}}}}\,$, it is also true that **Ĩ**_{a} = **Ĩ**_{b} = **Ĩ**_{c} and the phase angles of the currents will differ by ±120°. Consequently, it is possible to compute the power for each phase from the phase voltage and the associated line current. Denote the complex power for each phase by **S**, where:

\[\begin{matrix}\begin{align}& S=P+jQ \\& \overset{\tilde{\ }}{\mathop{I}}\,\cos \theta +j\overset{\tilde{\ }}{\mathop{V}}\,\overset{\tilde{\ }}{\mathop{I}}\,\sin \theta \\\end{align} & {} & (9) \\\end{matrix}\]

The total real power delivered to the balanced wye (star) load is 3P, and the total reactive power is 3Q. The total complex power **S**_{T} is

\[\begin{matrix}\begin{align}& {{S}_{T}}={{P}_{T}}+j{{Q}_{T}}=3P+j3Q \\& =\sqrt{{{(3P)}^{2}}+{{(3Q)}^{2}}}\angle \theta \\\end{align} & {} & (10) \\\end{matrix}\]

The apparent power |**S**_{T}**|** is:

\[\begin{matrix}\begin{align}& \begin{matrix}\left| {{S}_{T}} \right| & =3\sqrt{{{(\overset{\tilde{\ }}{\mathop{V}}\,\overset{\tilde{\ }}{\mathop{I}}\,)}^{2}}{{\cos }^{2}}\theta +{{(\overset{\tilde{\ }}{\mathop{V}}\,\overset{\tilde{\ }}{\mathop{I}}\,)}^{2}}{{\sin }^{2}}\theta } \\\end{matrix} \\& =3\overset{\tilde{\ }}{\mathop{V}}\,\overset{\tilde{\ }}{\mathop{I}}\, \\\end{align} & {} & (11) \\\end{matrix}\]

Such that:

\[\begin{matrix}\begin{align}& {{P}_{T}}=\left| {{S}_{T}} \right|\cos \theta \\& {{Q}_{T}}=\left| {{S}_{T}} \right|\sin \theta \\\end{align} & {} & (12) \\\end{matrix}\]

It is also possible to assemble a balanced load in a delta configuration. A wye (star) generator and a delta load are shown in **Figure 5**.

**Figure 5 **Balanced wye (star) generators with balanced delta load

Note immediately that each impedance **Z**_{Δ} sees a corresponding line voltage, rather than a phase voltage. For example, the voltage across **Z**_{c′a′} is $\overset{\tilde{\ }}{\mathop{{{V}_{ca}}}}\,$. Thus, the three load currents are:

\[\begin{align}& {{\overset{\sim }{\mathop{I }}\,}_{ab}}=\frac{{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{ab}}}}{{{\text{ }\!\!Z\!\!\text{ }}_{\text{ }\!\!\Delta\!\!\text{ }}}}=\frac{\sqrt{3}\overset{\tilde{\ }}{\mathop{V}}\,\angle (\pi /6)}{\left| {{Z }_{\Delta }} \right|\angle \theta } \\& {{\overset{\sim }{\mathop{I }}\,}_{bc}}=\frac{{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{bc}}}}{{{\text{ }\!\!Z\!\!\text{ }}_{\text{ }\!\!\Delta\!\!\text{ }}}}=\frac{\sqrt{3}\overset{\tilde{\ }}{\mathop{V}}\,\angle (-\pi /2)}{\left| {{Z }_{\Delta }} \right|\angle \theta }\begin{matrix}{} & {} & (13) \\\end{matrix} \\& {{\overset{\sim }{\mathop{I }}\,}_{ca}}=\frac{{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{ca}}}}{{{\text{ }\!\!Z\!\!\text{ }}_{\text{ }\!\!\Delta\!\!\text{ }}}}=\frac{\sqrt{3}\overset{\tilde{\ }}{\mathop{V}}\,\angle (5\pi /6)}{\left| {{Z }_{\Delta }} \right|\angle \theta } \\\end{align}\]

The relationship between a delta load and a wye (star) load can be illustrated by determining the delta load **Z**_{Δ} that would draw the same amount of current as a wye (star) load **Z*** _{y}* assuming a given source voltage. Consider the circuits shown in

\[{{({{\overset{\tilde{\ }}{\mathop{I }}\,}_{a}})}_{y}}=\frac{{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{an}}}}{\text{ }\!\!Z\!\!\text{ }}=\frac{\overset{\tilde{\ }}{\mathop{V}}\,}{\left| {{Z }_{y}} \right|}\angle (-\theta )\begin{matrix}{} & {} & (14) \\\end{matrix}\]

The current drawn by a delta load is:

\[\begin{matrix}\begin{align}& {{\text{(}{{\overset{\text{ }\!\!\tilde{\ }\!\!\text{ }}{\mathop{\text{ }\!\!I\!\!\text{ }}}\,}_{\text{a}}}\text{)}}_{\text{ }\!\!\Delta\!\!\text{ }}}\text{=}{{\overset{\text{ }\!\!\tilde{\ }\!\!\text{ }}{\mathop{\text{ }\!\!I\!\!\text{ }}}\,}_{\text{ab}}}\text{-}{{\overset{\text{ }\!\!\tilde{\ }\!\!\text{ }}{\mathop{\text{ }\!\!I\!\!\text{ }}}\,}_{\text{ca}}} \\& \text{=}\frac{{{\overset{\text{ }\!\!\tilde{\ }\!\!\text{ }}{\mathop{\text{V}}}\,}_{\text{ab}}}}{{{\text{ }\!\!Z\!\!\text{ }}_{\text{ }\!\!\Delta\!\!\text{ }}}}\text{-}\frac{{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{ca}}}}{{{\text{ }\!\!Z\!\!\text{ }}_{\text{ }\!\!\Delta\!\!\text{ }}}} \\& =\frac{\text{1}}{{{\text{ }\!\!Z\!\!\text{ }}_{\text{ }\!\!\Delta\!\!\text{ }}}}\text{(}{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{an}}}\text{-}{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{bn}}}\text{-}{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{cn}}}\text{+}{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{an}}}\text{)} \\& \text{=}\frac{\text{1}}{{{\text{ }\!\!Z\!\!\text{ }}_{\text{ }\!\!\Delta\!\!\text{ }}}}\text{(2}{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{an}}}\text{-}{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{bn}}}\text{-}{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{cn}}}\text{)} \\& =\frac{{{\overset{\tilde{\ }}{\mathop{\text{3V}}}\,}_{\text{an}}}}{{{\text{ }\!\!Z\!\!\text{ }}_{\text{ }\!\!\Delta\!\!\text{ }}}}\text{=}\frac{\text{3}{{\overset{\tilde{\ }}{\mathop{\text{V}}}\,}_{\text{an}}}}{\left| {{\text{ }\!\!Z\!\!\text{ }}_{\text{ }\!\!\Delta\!\!\text{ }}} \right|}\angle \text{(- }\!\!\theta\!\!\text{ )} \\\end{align} & {} & \text{(15)} \\\end{matrix}\]

The two currents (**Ĩ**_{a})_{Δ} and (**Ĩ**_{a})_{y} are equal if:

\[{{Z }_{\Delta }}=3{{Z }_{y}}\begin{matrix}{} & {} & (16) \\\end{matrix}\]

This result also implies that a delta load will draw three times as much current and absorb three times as much power as a wye (star) load with the same branch impedance.

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]]>

**Figure 1** Time and frequency domain representations of an AC circuit. The phase angle of the load is θ_{Z} = θ_{V} − θ_{I}.

The most general expressions for the voltage and current delivered to an arbitrary load are as follows:

\[\begin{matrix}\begin{align}& v(t)=V\cos (\omega t+{{\theta }_{V}}) \\& i(t)=I\cos (\omega t+{{\theta }_{I}}) \\\end{align} & {} & (1) \\\end{matrix}\]

Where *V* and *I* are the peak amplitudes of the sinusoidal voltage and current, respectively, and θ* _{V}* and θ

**Figure 2** Current and voltage waveforms with unit amplitude and a phase shift of 60°.

Notice that the current leads the voltage; or equivalently, the voltage lags the current. Keep in mind that all phase angles are relative to some reference, which is usually chosen to be the phase angle of a source. The reference phase angle is freely chosen and therefore usually set to zero for simplicity. Also keep in mind that a phase angle represents a time delay of one sinusoid relative to its reference sinusoid.

The instantaneous power dissipated by any element is the product of its instantaneous voltage and current.

\[\begin{matrix}p(t)=v(t)i(t)=VI\cos (\omega t+{{\theta }_{V}})\cos (\omega t+{{\theta }_{I}}) & {} & (2) \\\end{matrix}\]

This expression is further simplified with the aid of the trigonometric identity:

\[\begin{matrix}2\cos (x)cos(y)=\cos (x+y)+\cos (x-y) & {} & (3) \\\end{matrix}\]

Let *x=ωt + *θ* _{V}* and

\[\begin{matrix}\begin{align}& p(t)=\frac{VI}{2}[\cos (2\omega t+{{\theta }_{V}}+{{\theta }_{I}})+\cos ({{\theta }_{V}}-{{\theta }_{I}})] \\& =\frac{VI}{2}[\cos (2\omega t+{{\theta }_{V}}+{{\theta }_{I}})+\cos ({{\theta }_{Z}})] \\\end{align} & {} & \left( 4 \right) \\\end{matrix}\]

**Equation 4** illustrates that the total instantaneous power dissipated by an element is equal to the sum of a constant $\frac{1}{2}$VI cos (θ_{Z}) and a sinusoidal $\frac{1}{2}$ VI cos (2ωt + θ_{V} + θ_{I}), which oscillates at twice the frequency of the source. Since the time average of a sinusoid is zero over one period or over a sufficiently long interval, the constant $\frac{1}{2}$VI cos (θ_{Z}) is the time averaged power dissipated by a complex load Z, where θ_{Z} is the phase angle of that load.

**Figure 3** shows the instantaneous and average power corresponding to the voltage and current signals of **Figure 2**.

**Figure 3** Instantaneous and average power corresponding to the signals

These observations can be confirmed mathematically by noting that the time average of the instantaneous power is defined by:

\[\begin{matrix}{{P}_{avg}}\equiv \frac{1}{T}\int\limits_{{{t}_{0}}}^{{{t}_{0}}+T}{P(t)dt} & {} & (5) \\\end{matrix}\]

Where *T* is one period of *p*(*t*). Use **equation 4** to substitute for *p*(*t*) and yield:

\[\begin{matrix}\begin{align}& {{P}_{avg}}=\frac{1}{T}\int\limits_{{{t}_{0}}}^{{{t}_{0}}+T}{\frac{VI}{2}\left[ \cos (2\omega t+{{\theta }_{v}}+{{\theta }_{t}})+\cos ({{\theta }_{Z}}) \right]dt} \\& =\frac{VI}{2T}\int\limits_{{{t}_{0}}}^{{{t}_{0}}+T}{\left[ \cos (2\omega t+{{\theta }_{v}}+{{\theta }_{t}})+\cos ({{\theta }_{Z}}) \right]dt} \\\end{align} & {} & (6) \\\end{matrix}\]

The integral of the first part cos (2ωt + θ_{V} + θ_{I}) is zero while the integral of the second part (a constant) is T cos (θ_{Z}). Thus, the time averaged power P_{avg} is:

\[{{P}_{avg}}=\frac{VI}{2}\cos ({{\theta }_{Z}})=\frac{1}{2}\frac{{{V}^{2}}}{\left| Z \right|}\cos ({{\theta }_{Z}})=\frac{1}{2}{{I}^{2}}\left| Z \right|\cos ({{\theta }_{Z}})\begin{matrix}{} & (7) \\\end{matrix}\]

where

\[\left| Z \right|=\frac{\left| V \right|}{\left| I \right|}=\frac{V}{I}\begin{matrix}{} & and\begin{matrix}{} & {{\theta }_{Z}}={{\theta }_{V}}-{{\theta }_{I}}\begin{matrix}{} & (8) \\\end{matrix} \\\end{matrix} \\\end{matrix}\]

**Effective or Root Mean Square Value**

In North America, AC power systems operate at a fixed frequency of 60 cycles per second, or hertz (Hz), which corresponds to an angular (radian) frequency ω given by:

\[\begin{matrix}\omega =2\pi .60=377rad/s & AC\text{ }power\text{ }frequency & (9) \\\end{matrix}\]

It is customary in AC power analysis to employ the *effective* or *root*–*mean*–*square* (rms) amplitude rather than the peak amplitude for AC voltages and currents. In the case of a sinusoidal waveform, the effective voltage $\overset{\tilde{\ }}{\mathop{V}}\,\equiv {{V}_{rms}}$ is related to the peak voltage *V* by:

\[\begin{matrix}\overset{\sim }{\mathop{V}}\,={{V}_{rms}}=\frac{V}{\sqrt{2}} & {} & (10) \\\end{matrix}\]

Likewise, the effective current $\overset{\tilde{\ }}{\mathop{I}}\,\equiv {{I}_{rms}}$ is related to the peak current *I* by:

\[\begin{matrix}\overset{\sim }{\mathop{I}}\,={{I}_{rms}}=\frac{I}{\sqrt{2}} & {} & (11) \\\end{matrix}\]

The rms, or effective, value of an AC source is the DC value that produces the same average power to be dissipated by a common resistor.

The average power can be expressed in terms of effective voltage and current by plugging

$\begin{matrix} V=\sqrt{2}\overset{\tilde{\ }}{\mathop{V}}\, & and & I=\sqrt{2}\overset{\tilde{\ }}{\mathop{I}}\, \\\end{matrix}$

into **equation 7** to find:

\[\begin{matrix}{{P}_{avg}}=\overset{\sim }{\mathop{V}}\,\overset{\sim }{\mathop{I}}\,\cos ({{\theta }_{Z}})=\frac{\overset{\tilde{\ }}{\mathop{{{V}^{2}}}}\,}{\left| Z \right|}\cos ({{\theta }_{Z}})=\overset{\sim }{\mathop{{{I}^{2}}}}\,\left| Z \right|\cos ({{\theta }_{Z}}) & {} & (12) \\\end{matrix}\]

Voltage and current phasors are also represented with effective amplitudes by the notation:

\[\overset{\tilde{\ }}{\mathop{\text{V}}}\,=\overset{\tilde{\ }}{\mathop{V}}\,{{e}^{j{{\theta }_{V}}}}=\overset{\tilde{\ }}{\mathop{V}}\,\angle {{\theta }_{V}}\begin{matrix}{} & (13) \\\end{matrix}\]

AND

\[\overset{\tilde{\ }}{\mathop{\text{I}}}\,=\overset{\tilde{\ }}{\mathop{I}}\,{{e}^{j{{\theta }_{V}}}}=\overset{\tilde{\ }}{\mathop{I}}\,\angle {{\theta }_{I}}\begin{matrix}{} & (14) \\\end{matrix}\]

It is critical to pay close attention to the mathematical notation, namely that complex quantities, such as **V**, **I**, and **Z** are boldface. On the other hand, scalar quantities, such as *V, I*,$\overset{\tilde{\ }}{\mathop{V}}\,$ and $\overset{\tilde{\ }}{\mathop{I}}\,$are italic.

**Impedance Triangle**

**Figure 4** illustrates the concept of the impedance triangle, which is an important graphical representation of impedance as a vector in the complex plane.

**Figure 4** Impedance triangle

Basic trigonometry yields:

\[R=\left| \text{ }\!\!Z\!\!\text{ } \right|\cos \theta \begin{matrix}{} & (15) \\\end{matrix}\]

\[X=\left| \text{ }\!\!Z\!\!\text{ } \right|\sin \theta \begin{matrix}{} & (16) \\\end{matrix}\]

where *R* is the *resistance* and *X* is the *reactance.* Notice that both *R* and *P*_{avg} are proportional to cos (*𝜃 _{Z}*), which suggests that a triangle similar to (i.e., the same shape as) the impedance triangle could be constructed with

**Power Factor**

The phase angle *𝜃 _{Z}* of the load impedance plays a very important role in AC power circuits. From

\[\begin{matrix}{{\theta }_{Z}}=0 & \to & pf=1 & \begin{matrix}\text{Resistive Load} & (17) \\\end{matrix} \\\end{matrix}\]

For purely inductive or capacitive loads:

\[\begin{matrix}{{\theta }_{Z}}=+\pi /2 & \to & pf=0 & \begin{matrix}Inductive\text{ }Load & (18) \\\end{matrix} \\\end{matrix}\]\[\begin{matrix}{{\theta }_{Z}}=-\pi /2 & \to & pf=0 & \begin{matrix}Capacitive\text{ }Load & (19) \\\end{matrix} \\\end{matrix}\]

For loads with non-zero resistive (real) and reactive (imaginary) parts:

\[\begin{matrix}0<\left| {{\theta }_{Z}} \right|<\pi /2 & \to & \begin{matrix}0<pf<1 & \begin{matrix}Complex\text{ }Load & (20) \\\end{matrix} \\\end{matrix} \\\end{matrix}\]

Using the definition pf = cos(*𝜃 _{Z}*) the average power can be expressed as:

\[{{P}_{avg}}=\overset{\tilde{\ }}{\mathop{V}}\,\overset{\tilde{\ }}{\mathop{I}}\,pf\begin{matrix}{} & {} & (21) \\\end{matrix}\]

Thus, average power dissipated by a resistor is:

\[{{({{P}_{avg}})}_{R}}=\overset{\tilde{\ }}{\mathop{{{V}_{R}}}}\,\overset{\tilde{\ }}{\mathop{{{I}_{R}}}}\,p{{f}_{R}}=\overset{\tilde{\ }}{\mathop{{{V}_{R}}}}\,\overset{\tilde{\ }}{\mathop{{{I}_{R}}}}\,\begin{matrix}{} & (22) \\\end{matrix}\]

Because pf* _{R}* = 1. By contrast, the average power dissipated by a capacitor or inductor is:

\[{{({{P}_{avg}})}_{X}}=\overset{\tilde{\ }}{\mathop{{{V}_{X}}}}\,\overset{\tilde{\ }}{\mathop{{{I}_{X}}}}\,p{{f}_{X}}=0\begin{matrix}{} & (23) \\\end{matrix}\]

Because pf_{X} = 0, where the subscript X indicates a reactive element (i.e., either a capacitor or inductor). It is important to note that although capacitors and inductors are lossless (i.e., they store and release energy but do not dissipate energy), they do influence power dissipation in a circuit by affecting the voltage across and the current through resistors in the circuit.

When θz is positive, the load is inductive and the power factor is said to be lagging; when θz is negative, the load is capacitive and the power factor is said to be leading.

It is important to keep in mind that pf = cos(θ_{Z}) = cos(−θ_{Z}) because the cosine is an even function. Thus, while it may be important to know whether a load is inductive or capacitive, the value of the power factor only indicates the extent to which a load is inductive or capacitive.

To know whether a load is inductive or capacitive, one must know whether the power factor is leading or lagging.

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]]>\[\begin{matrix}{{\left| \frac{{{A}_{0}}}{{{A}_{i}}} \right|}_{dB}}=20{{\log }_{10}}\left| \frac{{{A}_{0}}}{{{A}_{i}}} \right|=20{{\log }_{10}}\left| \frac{{{A}_{0}}}{{{A}_{i}}} \right| & {} & (1) \\\end{matrix}\]

While logarithmic plots may at first seem a daunting complication, they have two significant advantages:

1. The product of terms in a frequency response function becomes a sum of terms because log(*ab/c*) = log(*a*) + log(*b*) − log(*c*). The advantage here is that Bode (logarithmic) plots can be constructed from the sum of individual plots of individual terms. Moreover, there are only four distinct types of terms present in any frequency response function:

a. A constant *K*.

b. Poles or zeros “at the origin”(*jω*).

c. Simple poles or zeros (1 + *jωτ*) or (1 + *jω/ω _{o}*).

d. Quadratic poles or zeros [1+ *jωτ* +(*jω/ω _{n}*)

2. The individual Bode plots of these four distinct terms are all well approximated by linear segments, which are readily summed to form the overall Bode plot of more complicated frequency response functions.

Consider the RC low-pass filter. The frequency response function is:

\[\frac{{{V}_{0}}}{{{V}_{i}}}(j\omega )=\frac{1}{1+j\omega /{{\omega }_{0}}}=\frac{1}{\sqrt{1+{{(\omega /{{\omega }_{0}})}^{2}}}}\angle -{{\tan }^{-1}}\left( \frac{\omega }{{{\omega }_{0}}} \right)\begin{matrix}{} & (2) \\\end{matrix}\]

where the circuit time constant is τ = *RC* = 1/*ω _{0}* and

**Figure 1** shows the Bode magnitude and phase plots for the filter.

**Figure 1** Bode plots for a low-pass *RC* filter; the frequency variable is normalized to *ω*/*ω*0. (a) Magnitude response; (b) phase angle response

The normalized frequency on the horizontal axis is *ωτ*. The magnitude plot is obtained from the logarithmic form of the absolute value of the frequency response function.

\[{{\left| \frac{{{V}_{0}}}{{{V}_{i}}} \right|}_{dB}}=20{{\log }_{10}}\frac{\left| K \right|}{\left| 1+j\omega \tau \right|}=20{{\log }_{10}}\frac{\left| K \right|}{\left| 1+j\omega /{{\omega }_{0}} \right|}\begin{matrix}{} & (3) \\\end{matrix}\]

When *ω ≪ ω _{0}*, the imaginary part of the simple pole is much smaller than its real part, such that |1 +

\[\begin{matrix}{{\left| \frac{{{V}_{0}}}{{{V}_{i}}} \right|}_{dB}}\approx 20{{\log }_{10}}K-20{{\log }_{10}}1=20{{\log }_{10}}K & (dB) & (4) \\\end{matrix}\]

Thus, at very low frequencies (*ω ≪ ω _{0}*),

When *ω ≫ ω*_{0}, the imaginary part of the simple pole is much larger than its real part, such that |1 + *jω/ω _{0}| ≈ | jω/ω_{0}*| = (

\[\begin{matrix}{{\left| \frac{{{V}_{0}}}{{{V}_{i}}} \right|}_{dB}}\approx 20{{\log }_{10}}K-20{{\log }_{10}}\frac{\omega }{{{\omega }_{0}}} & {} & {} \\{} & {} & (5) \\\approx 20{{\log }_{10}}K-20{{\log }_{10}}\omega +20{{\log }_{10}}{{\omega }_{0}} & {} & {} \\\end{matrix}\]

Thus, at very high frequencies (*ω ≫ ω _{0}*),

Finally, when *ω = ω _{0}*, the real and imaginary parts of the simple pole are equal, such that |1 +

\[20{{\log }_{10}}\frac{\left| K \right|}{\left| 1+j\omega /{{\omega }_{0}} \right|}=20{{\log }_{10}}K-20\log \sqrt{2}=20{{\log }_{10}}K-3dB\begin{matrix}{} & (6) \\\end{matrix}\]

Thus, the Bode magnitude plot of a **first-order low-pass filter** is approximated by two straight lines intersecting at *ω _{0}*.

The phase angle of the frequency response function $\angle \left( \frac{{{V}_{o}}}{{{V}_{i}}} \right)=-{{\tan }^{-1}}\left( \frac{\omega }{{{\omega }_{o}}} \right)$ has the following properties:

As a first approximation, the phase angle can be represented by three straight lines:

- For ω < 0.1ω
_{o}, ∠ (V_{o}/V_{i}) ≈ 0. - For 0.1 ω
_{o}and 10ω_{o}, ∠ (V_{o}/V_{i}) ≈ – (π/4) log (10ω/ω_{o}). - For ω > 10ω
_{o}, ∠ (V_{o}/V_{i}) ≈ –pi/2.

These straight-line approximations are illustrated in **Figure 1(b).**

**Table 1** lists the differences between the actual and approximate Bode magnitude and phase plots. Note that the maximum difference in magnitude is 3 dB at the cutoff frequency; thus, the cutoff is often called the **3-dB frequency** or the *half-power frequency*.

**Table 1 **Correction factors for asymptotic approximation of first-order filter

ω/ω_{0} |
Magnitude response error, (dB) |
Phase response error (deg) |

0.1 | 0 | −5.7 |

0.5 | −1 | 4.9 |

1 | −3 | 0 |

2 | −1 | −4.9 |

10 | 0 | +5.7 |

The case of an ** RC high-pass filter** is analyzed in the same manner as was done for the

\[\begin{matrix}\frac{{{V}_{0}}}{{{V}_{0}}}=\frac{j\omega CR}{1+j\omega CR}=\frac{j(\omega /{{\omega }_{0}})}{1+j(\omega /{{\omega }_{0}})} & {} & {} \\=\frac{(\omega /{{\omega }_{0}})\angle (\pi /2)}{\sqrt{1+{{(\omega /{{\omega }_{0}})}^{2}}}\angle \arctan (\omega /{{\omega }_{0}})} & {} & (7) \\=\frac{\omega /{{\omega }_{0}}}{\sqrt{1+{{(\omega /{{\omega }_{0}})}^{2}}}}\angle \left( \frac{\pi }{2}-\arctan \frac{\omega }{{{\omega }_{0}}} \right) & {} & {} \\\end{matrix}\]

**Figure 2** depicts the Bode plots for **equation 7**, where the horizontal axis indicates the normalized frequency *ω/ω _{0}*. Straight-line asymptotic approximations may again be determined easily at low and high frequencies. The results are very similar to those for the first-order low-pass filter.

For *ω < ω _{0}*, the Bode magnitude approximation intercepts the origin (

**Figure 2** Bode plots for RC high-pass filter. (a) Magnitude response; (b) phase response

The straight- line approximations of the Bode phase plot are:

- For
*ω*< 0.1*ω*, ∠ (V_{o}_{o}/V) ≈ π/2._{i} - 2. For 0.1ω
_{o}and 10ω_{o}, ∠ (V_{o}/V≈ − (π/4) log (10_{i)}*ω*/*ω*)._{o} - For
*ω > 10ω*, ∠ (V_{o}/V_{o}) ≈ 0._{i}

These straight-line approximations are illustrated in **Figure 2(b).**

Bode plots of high-order systems may be obtained by combining Bode plots of factors of the higher-order frequency response function. Let, for example,

\[H (j\omega )={{H }_{1}}(j\omega ){{H }_{2}}(j\omega ){{H }_{3}}(j\omega )\begin{matrix}{} & {} & ( \\\end{matrix}8)\]

which can be expressed, in logarithmic form, as

\[{{\left| H (j\omega ) \right|}_{dB}}={{\left| {{H }_{1}}(j\omega ) \right|}_{dB}}+{{\left| {{H }_{2}}(j\omega ) \right|}_{dB}}+{{\left| {{H }_{3}}(j\omega ) \right|}_{dB}}\begin{matrix}{} & {} & ( \\\end{matrix}9)\]

And

\[\angle H (j\omega )=\angle {{H }_{1}}(j\omega )+\angle {{H }_{2}}(j\omega )+\angle {{H }_{3}}(j\omega )\begin{matrix}{} & {} & ( \\\end{matrix}10)\]

Consider as an example the frequency response function

\[H (j\omega )=\frac{j\omega +5}{(j\omega +10)(j\omega +100)}\begin{matrix}{} & {} & (11) \\\end{matrix}\]

The first step in computing the asymptotic approximation consists of factoring each term in the expression so that it appears in the form a_{i} ( jω/ω_{i} +1), where the frequency ω* _{i}* corresponds to the appropriate 3-dB frequency, ω

\[\begin{matrix}H (j\omega )=\frac{5(j\omega /5+1)}{10(j\omega /10+1)100(j\omega /100+1)} & {} & {} \\{} & {} & (12) \\\frac{0.005(j\omega /5+1)}{10(j\omega /10+1)100(j\omega /100+1)}=\frac{K(j\omega /{{\omega }_{1}}+1)}{(j\omega /{{\omega }_{2}}+1)(j\omega /{{\omega }_{3}}+1)} & {} & {} \\\end{matrix}\]

**Equation 12** can now be expressed in logarithmic form:

\[\begin{matrix}H (j\omega ){{\left| _{dB}=\left| 0.005 \right| \right.}_{dB}}+\left| \frac{j\omega }{5}+1 \right|-\left| \frac{j\omega }{10}+1 \right|-\left| \frac{j\omega }{100}+1 \right| & {} & {} \\{} & {} & (13) \\\angle H (j\omega )=\angle 0.005+\angle \left( \frac{j\omega }{5}+1 \right)-\angle \left( \frac{j\omega }{10}+1 \right)-\angle \left( \frac{j\omega }{5}+1 \right) & {} & {} \\\end{matrix}\]

Each of the terms in the logarithmic **magnitude expression** can be plotted individually.

The constant corresponds to the value −46 dB, plotted in **Figure 3(a)** as a line of zero slope.

The numerator term, with a 3-dB frequency *ω _{1}* = 5, is expressed in the form of the first-order Bode plot of

You see that the individual factors are very easy to plot by inspection once the frequency response function has been normalized in the form of **equation 9.**

If we now consider the **phase response portion** of **equation 13,** we recognize that the first term, the phase angle of the constant, is always zero.

The numerator first-order term, on the other hand, can be approximated, that is, by drawing a straight line starting at 0.1ω_{1} =0.5, with slope +π/4rad/decade *(positive because this is a numerator factor)* and ending at 10ω_{1} = 50, where the asymptote +π/2 is reached.

The two denominator terms have similar behavior, except for the fact that the slope is −π/4 and that the straight line with slope −π/4 rad/decade extends between the frequencies 0.1ω_{2 }and 10ω_{2}, and 0.1ω_{3} and 10ω_{3}, respectively.

**Figure 3** depicts the asymptotic approximations of the individual factors in **equation 13**, with the magnitude factors shown in **Figure 3(a)** and the phase factors in **Figure 3(b).** When all the asymptotic approximations are combined, the complete frequency response approximation is obtained.

**Figure 4** depicts the results of the asymptotic Bode approximation when compared with the actual frequency response functions.

**Figure 3** Bode plot approximation for a second-order frequency response function. (a) Straight-line approximation of magnitude response; (b) straight-line approximation of phase angle response

**Figure 4** Comparison of Bode plot approximation with the actual frequency response function. (a) Magnitude response of second-order frequency response function; (b) phase angle response of second-order frequency response function.

You can see that once a frequency response function is factored into the appropriate form, it is relatively easy to sketch a good approximation of the Bode plot, even for higher-order frequency response functions.

This section illustrates the Bode plot asymptotic approximation construction procedure. The method assumes that there are no complex conjugate factors in the response and that both the numerator and denominator can be factored into first-order terms with real roots.

1. Express the frequency response function in factored form, resulting in an expression similar to the following:

\[H\left( j\omega \right)=\frac{K\left( {j\omega }/{{{\omega }_{1}}+1}\; \right)\cdots \left( {j\omega }/{{{\omega }_{m}}+1}\; \right)}{\left( {j\omega }/{{{\omega }_{m+1}}+1}\; \right)\cdots \left( {j\omega }/{{{\omega }_{n}}+1}\; \right)}\]

2. Select the appropriate frequency range for the semi logarithmic plot, extending at least a decade below the lowest 3-dB frequency and a decade above the highest 3-dB frequency.

3. Sketch the magnitude and phase response asymptotic approximations for each of the first-order factors, using the techniques illustrated in **Figures 1 to 4**.

4. Add, graphically, the individual terms to obtain a composite response.

5. If desired, apply the correction factors of **Table 1**.

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